Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal – Responsive to electromagnetic radiation
Reexamination Certificate
2001-09-27
2002-09-24
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making device or circuit responsive to nonelectrical signal
Responsive to electromagnetic radiation
C438S144000
Reexamination Certificate
active
06455345
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a charge transfer device for use in, for example, a solid-state image sensor or a delay element, and a manufacturing process therefor.
2. Description of the Related Art
A conventional charge transfer device for use in, for example, a solid-state image sensor or a delay element is shown in FIG.
6
. FIGS.
6
(
a
),
6
(
b
) and
6
(
c
) respectively are a schematic plan view, a schematic cross section taken on line VI(b)—VI(b) of FIG.
6
(
a
), and a schematic cross section taken on line VI(c)—VI(c), which are disclosed in JP-A 57-7964.
In an n-type silicon substrate
1
, there is a p-type well
2
in which there is an n-type well
3
in which a charge transfer channel is to be formed. There are n+ regions
4
containing an n-type dopant at a higher concentration than that in the n-type well
3
, on both sides of the n-type well
3
along its charge transfer direction (the direction of line X-X′ in the figure), and around the n+ region
4
, a p+ channel stopper
7
is formed. On the n-type well
3
and the n+ region
4
, there are a number of gate electrodes
6
via a gate insulator
5
consisting of, for example, an oxide film such as SiO
2
.
FIG. 7
shows an electric potential distribution along line Z-Z′ of FIG.
6
(
c
), i.e., the depth direction, where a lower position has a higher potential. In this figure, the origin of the depth direction is the silicon/gate insulator interface, and as a specific example, 0 V is applied to the p+ channel stopper
7
and the p-type well
2
and a lower (VL) or higher voltage (VH) to the gate electrode
6
. To the n-type silicon substrate
1
, a voltage with a reverse bias to the p-type well
2
is applied. The highest potential in the potential distribution along the depth direction shown in
FIG. 7
, is referred to as a “channel potential”.
When a higher voltage (VH) is applied to a gate and a lower voltage (VL) is to two adjacent gates, electrons are transferred to beneath the gate electrode to which the VH is applied, causing a potential reduction. The potential may be reduced to the channel potential of the adjacent gate electrodes to which the VL is applied. The dotted line in this figure indicates the potential distribution at this time. An electric charge which may cause the potential change is the maximum transferable charge.
By reference to FIGS.
8
(
a
),
8
(
b
) and
8
(
c
), a process for charge transfer in the charge transfer device shown in FIG.
6
(
a
)-
6
(
c
) will be described. FIG.
8
(
a
) is the same schematic cross section as that shown in FIG.
6
(
b
). FIG.
8
(
b
) shows a channel potential distribution along line VIII(b)—VIII(b) of FIG.
8
(
a
) at each time indicated in FIG.
8
(
c
) FIG.
8
(
c
) shows timing of a voltage pulse applied to the gate electrode of the charge transfer device. FIGS.
8
(
a
) and
8
(
b
) are depicted in a manner that they horizontally have the same position, and in FIG.
8
(
b
) a lower position has a higher potential. To electrodes 4V1 to 4V4 is applied a binary pulse varying between the higher (VH) and the lower (VL) voltages as shown in FIG.
8
(
c
).
The lower voltage is a voltage (pinning voltage) by which positive holes are stored in the silicon/oxide film interface to make the interface potential 0 V. In this manner, a dark current occurring via a silicon/oxide film interface level may be minimized.
The higher voltage is a voltage which is below the channel potential when the lower voltage is applied. Thus, a transferred charge does not reach the silicon/oxide film interface even when a maximum transferable charge (Qmax) is transferred, and is not trapped on the interface level. The charge can be, therefore, transferred without reduction of a transfer efficiency.
First, at time T1, the higher voltage (VH) is applied to &phgr;V1 and &phgr;V2 electrodes, and the channel potential increases beneath the electrodes, to cause charge storage. The stored charge is indicated by the slanted line in FIG.
8
(
b
). At time T2, &phgr;V3 is at the higher voltage (VH) while &phgr;V1 at the lower voltage (VL), and thus, a charge is transferred to beneath the electrodes &phgr;V2 and &phgr;V3. In a similar manner, at T3 and T4, a charge is transferred to beneath electrodes &phgr;V3 and &phgr;V4 and electrodes &phgr;V4 and &phgr;V1, respectively. Then, at T5, a charge is transferred to beneath electrodes &phgr;V1 and &phgr;V2, returning to the state at Ti except that a charge is moved to the right, i.e., beneath the electrodes &phgr;V1 and &phgr;V2. By repeating the above process, a charge is sequentially transferred to the right direction. Such charge transfer is indicated by a right oblique downward arrow in FIG.
8
(
b
).
Next, the reason why the maximum transferable charge (Qmax) is increased by the charge transfer device shown in FIGS.
6
(
a
)-
6
(
c
), will be described. FIG.
9
(
a
) is a cross section taken on line IX(a)—IX(a) of FIG.
6
(
a
). FIG.
9
(
b
) shows a channel potential distribution along line IX(b)—IX(b) of FIG.
9
(
a
) when a lower (VL) or higher (VH) voltage is applied, where the dotted line indicates a distribution for a charge transfer device without an n+ region. FIG.
9
(
a
) shows a capacity at the local maximum of the potential (channel position) in the n-type well
3
when a voltage VG is applied to the gate electrode. A capacity between the channel position and the gate electrode (Cs) is the sum of serial connection of the gate insulator capacity and the capacity in the silicon from the silicon/gate insulator interface to the channel position. A capacity of both sides (Ccs) is one between the channel position and the p+ channel stopper
7
. A capacity below the channel position (Cb) is one between the channel position and the p-type well
2
.
When a voltage VG is applied to the gate electrode and 0 V is to the p+ channel stopper
7
and the p-type well
2
, relationship between a variation of the channel potential &Dgr;&phgr;ch and a variation of the gate voltage &Dgr;VG can be represented by the following equation:
&Dgr;&phgr;ch=&Dgr;VG·Cs/
(
Cs+
2
Ccs+Cb
)
A charge stored beneath the gate electrode can be substantially represented by the following equation:
Δ
Q
=
Δφ
ch
·
(
Cs
+
2
Ccs
+
Cb
)
=
Δ
VG
·
Cs
(
1
)
A value obtained by integrating the above Equation (1) with the variation (amplitude) of the gate electrode is the maximum transferable charge (Qmax). It will be understood that when the amplitude is constant, a larger Cs gives a larger Qmax.
The solid line in FIG.
9
(
b
) indicating the channel potential distribution along line V-V′ when a lower (VL) or higher (VH) voltage is applied to the gate electrode, will be referred. The horizontal position is matched with the corresponding position in FIG.
9
(
a
).
A concentration and a width in the n+ region
4
is adjusted so that when the lower voltage (VL) is applied, the curved channel potential line is changed within the n+ region
4
to be straight throughout the n-type well
3
. When the higher voltage (VH) is applied, a depletion layer formed by p-n junction between the p+ channel stopper
7
and the n+ region
4
is extended to enter the n-type well
3
. The straight part of the channel potential is, therefore, shorter than one when the lower voltage (VL) is applied. A capacity between the straight part of the channel potential and the gate electrode is Cs, which contributes a charge as indicated by Equation (1). On the other hand, the n+ region
4
forms p-n junction with the p+ channel stopper
7
, and a potential increases from 0 V on the stopper side to &phgr;ch. The capacity of this part is Ccs, which does not contribute charge according to Equation (1). Increase of the straight part of the channel potential, therefore, leads to increase of Qmax.
In FIG.
9
(
b
), the dotted line indicates a channel potential dist
Foley & Lardner
Lattin Christopher
NEC Corporation
Niebling John F.
LandOfFree
Charge transfer device and a manufacturing process therefor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Charge transfer device and a manufacturing process therefor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Charge transfer device and a manufacturing process therefor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2908413