Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
2001-08-29
2003-02-04
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S238000, C257S241000, C257S214000, C257S215000
Reexamination Certificate
active
06515318
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a charge transfer device and more particularly to the charge transfer device that can be suitably used in an image pickup apparatus such as a television camera or a like.
The present application claims priority of Japanese Patent Application No. 2000-275708 filed on Sep. 11,2000, which is hereby incorporated by reference.
2. Description of the Related Art
FIG. 7
is a schematic block diagram for showing configurations of a conventional charge transfer device disclosed in Japanese Patent No. 2666522. The disclosed charge transfer device includes a CCD (Charge Coupled Device)
1
, a floating diffusion region
2
, depletion type n-channel MOS (Metal Oxide Silicon) transistors
3
to
5
and enhancement type n-channel MOS transistors
6
to
8
.
The floating diffusion region layer
2
is formed using a pn-junction islands-structured semiconductor region and is adapted to convert a signal charge (electron) injected into one terminal (charge injecting point P) of the floating diffusion region layer
2
after having been transferred through a charge transfer region (not shown) in the CCD
1
and after having passed a channel under an output gate (not shown), into a voltage. A capacitance of the floating diffusion region layer
2
, in order to enhance a conversion rate at which the above signal charge is converted into the voltage, is ordinarily set at as small as about 7 fF (femto Farad) . The MOS transistor
3
operates as a resetting unit to eject the signal charge accumulated in the floating diffusion region
2
and to reset a voltage V
P
at the charge injecting point P to a constant level, to a gate of which a reset pulse &phgr;
R
is fed and to a drain of which a reset drain voltage V
RD
is applied and a source of which is connected to the charge injecting point P.
The MOS transistors
4
,
6
, and
7
make up a first stage source follower
9
in which the MOS transistor
6
functions as a driving transistor, the MOS transistor
4
functions as a load transistor, and the MOS transistor
7
functions as the load transistor only when it is turned ON. An input terminal of the source follower
9
, that is, to a gate of the MOS transistor
6
, is connected to the charge injecting point P. A drain of the MOS transistor
6
is applied a supply voltage V
DD
. A gate and source of the MOS transistor
4
and a source of the MOS transistor
7
are grounded and to a gate of the MOS transistor
7
is applied the reset pulse &phgr;
R
.
The MOS transistors
5
and
8
make up a second stage source follower
10
in which the MOS transistor
8
functions as a driving transistor and the MOS transistor
5
functions as a load transistor. An input terminal of the source follower
10
, that is, a gate of the MOS transistor
8
is connected to an output terminal of the source follower
9
, that is, a connection point among the source of the MOS transistor
6
, drain of the MOS transistor
4
, and the drain of the MOS transistor
7
. To a drain of the MOS transistor
8
a supply voltage V
DD
is applied. A gate and source of the MOS transistor
5
are grounded. From an output terminal of the source follower
10
, that is, from a connection point between a source of the MOS transistor
8
and a drain of the MOS transistor
5
is an output voltage V
OUT
.
Next, operations of the above charge transfer device will be described. The signal charge (electron) transferred through the charge transfer region and accumulated under a transfer electrode, after having passed through the channel under the gate, is injected into the charge injecting point P of the floating diffusion region
2
. A voltage at the charge injecting point P that has changed by the injection of the signal charge into the charge injecting point P, after being amplified by each of the first stage and second stage source followers
9
and
10
, is output as the output voltage V
OUT
. The output voltage V
OUT
is further amplified about ten-fold and, after having been sample-held, is converted into digital data by an AD converter (not shown).
Then, when the reset pulse &phgr;
R
goes high, the MOS transistor
3
is turned ON and a source voltage of the MOS transistor
3
, that is, a voltage V
P
at the charge injecting point P and the reset drain voltage V
RD
that has been applied to a drain of the MOS transistor
3
become the same. At this point, in the source follower
9
, since the MOS transistor
7
is turned ON by the supply of the “high” reset pulse &phgr;
R
and the MOS transistors
4
and
7
forming the parallel circuit, function as the load transistors, more currents flow through the MOS transistors
4
and
7
, compared with the case in which only the MOS transistor
4
functions as the load transistor, thus causing an offset current of the source follower
9
to be reduced.
Next, when the reset pulse &phgr;
R
goes low, the MOS transistor
3
is turned ON and a state at the charge injecting point P becomes floating. At this point, in the source follower
9
, since the MOS transistor
7
is turned OFF by the supply of the “low” reset pulse &phgr;
R
and only the MOS transistor
4
functions as the load transistor, less current flows through the MOS transistor
4
, compared with the case in which the MOS transistors
4
and
7
forming the parallel circuit, function as the load transistor, thus causing the offset voltage of the source follower
9
to be boosted.
FIG. 8A
is a cross-sectional view of the floating diffusion region
2
and related components connected thereto to explain principles of occurrence of a reset field-through noise described later.
FIG. 8B
is a diagram showing potentials of the components making up the floating diffusion region
2
. In some cases, as shown in FIG.
7
and
FIGS. 8A and 8B
, since a coupling capacitor C
1
exists between a gate
3
a
of the MOS transistor
3
and the charge injecting point P, electrons accumulated under the gate
3
a
are returned back to the floating diffusion region
2
through this coupling capacitor C
1
. Moreover, the capacitance of the floating diffusion region
2
, as described above, is ordinarily set at as low as 7 fF to enhance the conversion rate to convert the signal charge to the voltage and, structurally, its impedance is very high. Moreover, as shown in FIG.
7
and
FIGS. 8A and 8B
, a coupling capacitor C
2
exists between the gate and the source of the MOS transistor
6
. As shown in
FIG. 8A
, an N-type well
12
is formed on a P-type well or P-type substrate
11
and a gate oxide film (not shown) and polycrystalline silicon film (not shown) are sequentially formed on a top surface of the N-type well
12
and, by performing patterning operations on them films, the CCD
1
, floating diffusion region
2
, and MOS transistor
3
are fabricated.
Due to the above three factors, the voltage V
P
at the charge injecting point P is changed in synchronization with switching operations of the MOS transistor
3
caused by the supply of the reset pulse &phgr;
R
, A noise induced by this change in the voltage is called the “reset field-through noise”. Though this reset field-through noise is superimposed on the output voltage V
OUT
, as described above, since only when the reset pulse &phgr;
R
goes high, the MOS transistor
7
functions as the load transistor and the offset voltage of the source follower
9
is lowered, the reset field-through noise superimposed on the output voltage V
OUT
, since it is reduced by the MOS transistor
7
, becomes small, compared with the reset field-through noise being produced in the voltage V
P
at the charge injecting point P.
In the conventional charge transfer device as described above, as the MOS transistor
5
making up the second stage source follower
10
, the depletion type MOS transistor is used. Since such the depletion type MOS transistor has the property that the current to be controlled does not flow at an interface surface of the gate oxide film thereof but flows at a deeper portion, the current control is structurally difficult a
Abraham Fetsum
Hayes & Soloway PC
NEC Corporation
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