Charge transfer device

Details Charge transfer device Charge transfer device

1999-01-29

2003-07-29

Boccio, Vincent (Department: 2615)

Television

Camera, system and detail

Solid-state image sensor

C327S142000, C327S091000, C257S239000, C250S208100, C377S060000

Reexamination Certificate

active

06600513

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a charge transfer device (CTD) having a charge detecting portion of a floating diffusion amplifier type (hereinafter, referred to as “FDA type”) preferable for an image sensor, a delay device, etc. More specifically, the present invention relates to a charge transfer device which is capable of decreasing a reset gate voltage in a charge voltage converting portion of a signal charge, realizing non-adjustment of a reset gate voltage, and thereby reducing the number of components in a system and power consumption.
2. Description of the Related Art
As a representative device using a CTD such as a charge coupled device (CCD), a two-dimensional image sensor shown in
FIG. 7
, a delay device of a serial-parallel-serial (SPS) system shown in
FIG. 8
, and the like are well-known.
In the two-dimensional image sensor shown in
FIG. 7
, a signal charge photoelectrically converted by photoelectric conversion elements
2
arranged in a matrix is transferred to a signal output portion
12
via a vertical transfer channel
6
and a horizontal transfer channel
8
. The transferred signal charge is charge-voltage converted at the signal output portion
12
and given to an amplifier (MOS amplifier)
14
. When the amplifier
14
is operated, an output signal is taken out. Thereafter, when a reset transistor (not shown) is operated, the signal output portion
12
is reset to a reference level V
RD
(power-supply voltage). Reference numeral
4
denotes a transfer gate.
In the delay device shown in
FIG. 8
, a signal charge given to a signal input portion
16
from an input terminal is transferred to a signal output portion
12
via a horizontal transfer channel
18
, a vertical transfer channel
6
, and a horizontal transfer channel
8
. Thereafter, an operation similar to that of the image sensor shown in
FIG. 7
is operated.
An example of a charge transfer device includes one which is provided with an FDA type charge detecting portion.
FIG. 9
shows a representative structural example of an FDA type charge detecting portion. This charge detecting portion includes a reset drain (RD)
22
, a reset gate (RG)
20
, an output gate (OG), a horizontal transfer gate
8
consisting of H
1
, H
2
, . . . , a floating diffusion (FD), and an amplifier (MOS amplifier)
14
. The reset drain
22
and the floating diffusion (FD) are a N
+
region formed in a p-type semiconductor substrate. The floating diffusion (FD) and the p-type semiconductor substrate are collectively referred to as a floating diode
24
.
FIG. 10
shows a drive timing of the charge detecting portion.
FIG. 11
is a diagram showing a potential relationship between the time and the potential.
FIG. 12
shows (V
G
−&PHgr;
max
) characteristics.
Herein, V&PHgr;
RLow
and V&PHgr;
RHigh
represent a “Low” level and a “High” level of a reset pulse applied to the reset gate
20
, as shown in FIG.
10
. &Dgr;V
max
in
FIG. 11
represents the maximum signal amplitude that can be handled by the floating diode
24
.
Assuming that a potential under the reset gate
20
is &PHgr;
max
(V
G
[V]) and a voltage applied to the reset drain
22
is V
RD
, &Dgr;V
max
is represented by the following Expression (1):
&Dgr;
V
max
=V
RD
−&PHgr;
max
(
V&PHgr;
RLow
)−&Dgr;
V
F
  (1)
wherein &Dgr;V
F
represents a field-through component of a signal output.
From the above expression, in order to perform a reset operation of the reset gate
20
, the following Expression (2) should be satisfied.
&PHgr;
max
(
V&PHgr;
RHigh
)−
V
RD
≧0  (2)
Furthermore, in the case where a reset gate pulse at a predetermined level is applied to the reset gate
20
from outside (outside of a device), when &PHgr;
max
and the voltage V
RD
applied to the reset drain
22
are under a predetermined condition, an amplitude and a level of a required reset gate pulse are, for example, as follows: in the case of V
RD
=15.0 V, &PHgr;
max
(V
G
=0 V)=8.9 V, &Dgr;&PHgr;
max
/&Dgr;V
G
=0.8, and &Dgr;V
F
=0.75 V, in order to satisfy &Dgr;V
max
≧1.2 V, the following Expression (3) should be satisfied:
V&PHgr;
RLow
≦5.1
V
  (3)
and in order to ensure a reset operation, the following Expression (4) should be satisfied:
V&PHgr;
RHigh
≧7.6
V
  (4).
Thus, if an amplitude of a reset pulse is at least 2.5 V (=7.6 V−5.1 V), a reset operation can be ensured.
However, there are in actuality variations in a potential under the reset gate
20
and in a power-supply voltage used in such a system due to the variations in the production processes of a device. Therefore, it is required to set an amplitude and a level of a reset gate pulse so as to simultaneously ensure &Dgr;V
max
and a reset operation, considering each variation.
As an example,
FIG. 13
shows (V
G
−&PHgr;
max
) characteristics of the reset gate
20
in the case where the variation of the potential &PHgr;
max
is ±0.7 V, and the variation of the voltage V
RD
to be applied to the reset drain
22
is ±0.5 V.
Under the conditions of V
RD
=15.0±0.5 V, &PHgr;
max
(V
G
=0 V)=8.9±0.7 V, &Dgr;&PHgr;
max
/&Dgr;V
G
=0.8, and &Dgr;V
F
=0.75 V, in order to satisfy &Dgr;V
max
≧1.2 V, the following Expression (5) should be satisfied:
V&PHgr;
RLow
≦3.6
V
  (5)
and in order to ensure a reset operation, the Expression (6) should be satisfied:
V&PHgr;
RHigh
≧9.1
V
  (6)
Thus, an amplitude of a reset pulse should be at least 5.5 V (=9.1 V−3.6 V).
A variation of ±0.7 V of the potential &PHgr;
max
corresponds to a reset pulse width of 1.75 V, and a variation of ±0.5 V of the voltage V
RD
applied to the reset drain
22
corresponds to a reset pulse width of 1.25 V. Therefore, a reset pulse width is required to be 3.0 V (=1.75 V+1.25 V) plus 2.5 V (=7.6 V−5.1 V; in the case of no variations).
Recently, for example, in a two-dimensional image sensor, there is a demand for a decrease in the drive voltage and in the number of components, in addition to the demand for further miniaturization of a device and reductions in power consumption.
In the past, an output from a timing IC is amplified by an external circuit, offset, and input to a device as a pulse applied to a reset gate of an FDA type charge detecting portion. Due to the demand for a decrease in the drive voltage, a reduction in the number of components of a system, and a reduction in power consumption, driving of a reset gate with a voltage of 3.3 V, a decrease in the drive voltage, and non-adjustment of an offset voltage are in demand.
However, in a conventional system in which a reset gate pulse at a predetermined level is applied from the outside, an offset voltage of a reset pulse is required to be applied and adjusted by an external circuit. Furthermore, regarding decreases in voltage, it is required to consider the variation (+0.7 V in
FIG. 13
) of a potential under a reset gate and the variation (±0.5 V in
FIG. 13
) of a voltage applied to a reset drain due to the variations of a process. This involves difficulty in control, so that sufficient V
max
and a reset operation cannot be ensured.
In order to overcome these problems, there is a method for obtaining an optimum point of a reset operation in the course of a wafer test and writing the measured value into a write circuit provided in a device. However, according to this method, a wafer test and a method for writing a measured value become undesirably complicated.
Another method is described in Japanese Laid-Open Publication No. 6-133227. According to this method, as shown in
FIG. 14
, a control circuit including a detecting transistor
51
having the same potential profile as that of a reset gate
20
of an FDA type charge detecting portion A is provided in a device, and fluctuation in a reset operation point caused by the fluctuation in potential under the r

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