Charge-sharing technique during flash memory programming

Details Charge-sharing technique during flash memory programming Charge-sharing technique during flash memory programming

2007-03-27

2007-03-27

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185250

Reexamination Certificate

active

11229530

ABSTRACT:
A non-volatile memory cell array, such as a Flash NOR array, is programmed by applying voltages to bit lines that connect to memory cells in the memory cell array. A first bit line corresponding to a first memory cell in the memory array may be turned on to perform a first programming operation for the first memory cell and second bit line corresponding to a second memory cell in the memory array may be turned on to perform a second programming operation that is configured to complete after the first programming operation. The turning on/off of the first and second bit lines may be overlapped to share charge between the first and second bit lines. This overlapping can reduce wasted power and decrease programming pulse overshoot problems.

REFERENCES:
patent: 6570790 (2003-05-01), Harari

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