Charge redistribution A/D converter with reduced small signal er

Details Charge redistribution A/D converter with reduced small signal er Charge redistribution A/D converter with reduced small signal er

1987-08-11

1989-05-16

Roskoski, Bernard

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341162, 341163, H03K 1302

Patent

active

048313815

ABSTRACT:
An A/D converter utilizing a charge redistribution scheme includes a single ended comparator and associated therewith a capacitor array of binary weighted capacitors. The input signal is sampled with the input of the comparator disposed at a point midway between ground and a unipolar reference voltage. The bottom plates of the capacitors in the hold mode are then disposed at the midpoint of the reference signal. In the redistribution mode, the value of the bits is determined by switching the bottom plates of the capacitors between the midpoint of the reference voltage and either ground or the full value of the reference voltage. The input signal during sampling is attenuated by sampling it onto only one-half of the array.

REFERENCES:
patent: 4200863 (1980-04-01), Hodges
patent: 4381496 (1983-04-01), Carter

Affiliated with

Also associated with

Rating

Charge redistribution A/D converter with reduced small signal er does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Charge redistribution A/D converter with reduced small signal er, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Charge redistribution A/D converter with reduced small signal er will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2326237