Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit
Reexamination Certificate
2000-12-15
2003-03-04
Le, Que T. (Department: 2878)
Radiant energy
Photocells; circuits and apparatus
Photocell controlled circuit
C250S2140RC
Reexamination Certificate
active
06528775
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to charge-reading circuits designed especially for the reading of charges picked up by solid-state image sensors.
2. Description of the Prior Art
These charge reading circuits are of the charge integrator type. Prior art read circuits
30
of this kind are shown in FIG.
1
. More particularly,
FIG. 1
shows an image sensor
1
with a plurality of photosensitive dots P
1
to P
9
each connected between a row conductor Y
1
to Y
3
and a column conductor X
1
to X
3
. Each photosensitive dot P
1
to P
2
is formed by a photosensitive diode Dp series-connected with a switch function element in the form of a selection-switching diode Dc. A transistor could have been used as a switch function element. The row conductors Y
1
to Y
3
are connected to at least one addressing device
3
while the column conductors X
1
to X
3
are connected to a read device CL comprising as many read circuits
30
as there are column conductors X
1
to X
3
. These read circuits
30
are capable, during an integrating operation, of converting charges into voltage. These charges are collected at the junction point A between the photosensitive diode Dp and the switch function element Dc of a photosensitive dot to which they are connected. This collecting of charges takes place when the photosensitive diodes Dp are in a receptive state and. the photosensitive dots are exposed to a piece of information to be sensed.
The reading of all the photosensitive dots connected to one and the same row conductor Y
1
to Y
3
is done at the same time, row conductor by row conductor. The photosensitive dots of one and the same column conductor X
1
to X
3
are read, each in turn, by the read circuit
30
connected to this column conductor.
It is sought to ensure that the conversion is done with a relationship of proportionality that is as constant as possible between the quantity of charges collected and the voltage delivered by the read circuit
30
so that the image delivered by the read device CL is as close as possible to the image to be detected.
Each read circuit
30
has an input E formed by one of the electrodes of the pair formed by the drain d and the source s of a read MOS transistor M
1
. This input E is connected to one of the column conductors X
1
to X
3
on which the collected charges flow. The output S of the read circuit
30
is obtained on the side that has the other electrode (source s or drain d) of the read MOS transistor M
1
which is connected to one of the plates of an integration capacitor C. The other plate receives a reference voltage VDR. There is a direct transfer of the charges injected into the input E of the read circuit
30
through the read MOS transistor M
1
and integration by the capacitor C if the transistor is conductive. The transfer of the charges can be accelerated by the application of a control voltage V
1
at the gate g of the read MOS transistor M
1
. This control voltage V
1
is delivered by an acceleration inverter amplifier A
1
whose input is connected to the input E of the read circuit
30
. The voltage V
1
is such that:
V
1
=−G×Ve
with Ve as the input voltage E of the read circuit
30
and G as the voltage gain of the amplifier A
1
. In practice, the gain G is high and is chosen for example to be between 500 and 1000 so as to reduce the noise associated with the transfer of the charges between the input E and the output S. The amplifier inverter A
1
is supplied with a negative supply voltage VR (for example in the range of −2.75 volts).
It is furthermore planned, in parallel with the capacitor C, to obtain a switch I in order to reinitialize it when all the charges coming from a photosensitive dot have been integrated and before integrating those coming from another photosensitive dot.
This type of read circuit
30
is a one-way circuit and this is a drawback because it can integrate only charges with a single type of polarity, namely either positive charges (holes) or negative charges (electrons). The type of polarity is conditioned by the nature of the channel of the read MOS transistor M
1
.
If the MOS transistor M
1
is an N channel transistor, the charges injected into the MOS transistor M
1
can be none other than electrons and the voltage VDR is more positive than the voltage Ve. If, instead of electrons, it is holes that are injected, the input voltage Ve becomes more positive then the reference voltage VDR and the control voltage V
1
then blocks or turns off the read MOS transistor M
1
. So long as the read MOS transistor M
1
is off, the charges injected into the input E of the read circuit
30
cannot be integrated and the pieces of information that they convey are then lost. The timing diagrams of
FIGS. 2
a
to
2
e
respectively show the forms of the quantity of charges reaching the input E of one of the read circuits
30
, the voltage Ve at the input E of the circuit, the control voltage V
1
applied to the gate g of the read MOS transistor M
1
, the voltage Vs at output S of the read circuit
30
and finally the state of the switch I which reinitializes the capacitor C. It is assumed that, in the example described, the MOS transistor M
1
is an N channel transistor and that the read circuit can read quantities of negative charges or electrons. If the transistor were a P channel transistor, it would be capable of reading holes, and the signs of the voltages and their direction of variation would be reversed in the following description.
When electron packets reach the input E of the read circuit, the voltage Ve at the input E of the circuit
30
decreases suddenly from a basic value Vb, the control voltage V
1
for its part starts rising from an initial value V
1
i up to a value V
1
d and the MOS transistor M
1
gets unblocked. The basic value Vb is equal to the sum of the supply voltage VR of the acceleration amplifier A
1
and the threshold voltage of the transistor included in the amplifier. The amplifier A
1
is not described in detail.
The charges can be integrated. The voltage Vs at the output S, initially taken to the value VDR, starts decreasing until it reaches the value Vs
1
after the integration of all the charges received. When all the charges are integrated, the voltage Ve at its input returns to its base value Vb, the voltage V
1
at the output also returns to the initial value V
1
i and the read MOS transistor M
1
goes off. The voltage Vs keeps the value Vs
1
reached so long as the resetting switch I remains open and then returns to the reference value VDR as soon as it is closed.
When a photosensitive dot is defective, i.e. when at least one of its components (photosensitive diode Dp or switch function element Dc) is out of operation, a large number of holes reaches the input E of the read circuit
30
to which it is connected. This number is generally far greater than the number of the electrons reaching a photosensitive dot in functioning condition even if it has been exposed TO A highly intense light flux. This arrival of holes is called reverse over-dazzling. The voltage Ve at input greatly increases. The control voltage V
1
which follows the variations in the voltage Ve at the input, in reversing and amplifying these variations, decreases sharply. The MOS transistor M
1
which was off or blocked remains blocked. The voltage Vs at the output S does not vary but remains at the reference value VDR. The closing of the resetting switch I has no effect on the voltage Vs at the output. When electrons reach the input E of the read circuit once again, the voltage Ve at the input decreases slightly and the control voltage V
1
decreases too, but this is not enough to unblock the read MOS transistor M
1
. The voltage Vs at the output does not vary and the information carried by the electrons that reach the input E is lost. At the input of the read circuit, at least as many electrons as holes must be recovered in order to unblock the read MOS transistor M
1
. In the image detected, this takes the form of a column portion tha
Le Que T.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Trixell S.A.S.
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