Charge pumping semiconductor memory

Details Charge pumping semiconductor memory Charge pumping semiconductor memory

1978-09-25

1980-09-16

Munson, Gene M.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 54, 357 59, 307238, 365154, H01L 2702, H01L 2904, H03K 500, G11C 1134

Patent

active

042233330

ABSTRACT:
There is provided a semiconductor memory apparatus comprising a plurality of memory cells collectively integrated on the same chip in a matrix array and each formed of a flip-flop circuit including a pair of driver MOS transistors, a pair of load MOS capacitors connected to the respective paired driver MOS transistors and address-selection MOS transistors connected to both output terminals of the flip-flop circuit. The memory cells arranged in a row direction are of the same pattern, the adjacent memory cells arranged in a column direction are made symmetrical with each other, the source of one of the paired driver MOS transistors of a given memory cell is connected to the source of the corresponding one of the paired driver MOS transistors of another memory cell disposed adjacent to the first-mentioned memory cell in a row direction, the gates of the driver MOS transistors and address-selection MOS transistors are formed by selectively etching a first polycrystalline silicon layer, and the paired MOS capacitors are constituted by a second polycrystalline layer mounted through an insulation layer over the respective drain regions of the paired driver MOS transistor.

REFERENCES:
patent: 3662356 (1972-05-01), Michon et al.
patent: 4091460 (1978-05-01), Schuermeyer et al.
patent: 4125854 (1978-11-01), McKenny et al.
Burke et al., "Charge Pump Random-Access Memory", IEEE Int. Solid-State Circuits Conf., (2/72), Dig. Tech. Papers, pp. 16-17.
Ebel et al., "A 4096-Bit High-Speed Emitter-Coupled-Logic (ECL) Compatible Random Access Memory", IEEE J. Solid-State Circuits, vol. 5C-10 (10/75) pp. 262-267.
Iizuka et al., "Electrically Alterable Avalanche-Injection-Type MOS Read-Only Memory With Stacked Gate Structure", IEEE Trans. Electron Devices vol. ED-23 (4/76), pp. 379-387.

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