Charge-pumping circuits for a low-supply voltage

Details Charge-pumping circuits for a low-supply voltage Charge-pumping circuits for a low-supply voltage

2001-02-08

2002-03-19

Kim, Jung Ho (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S537000

Reexamination Certificate

active

06359501

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to charge-pumping, and more particularly to charge-pumping circuits for a low-supply voltage, which can supply higher positive or negative voltage.
2. Description of the Prior Art
Because positive or negative biased voltage is applied to memory circuits, positive and negative voltage generation is essential in memory circuits. For SRAM or DRAM, it may be applied to reduce current leakage or decrease the time needed for charging and discharging the memory cells. In recent years, flash memory has become one of the major memory products. High positive or negative voltage is required for programming or erasing the flash memory cells. There has been a number of charge-pumping circuits available, but most of them are based on Dickson charge-pumping circuit, which was published in ┌On-Chip High-Voltage generation in NMOS integrated circuits using an improvement voltage multiplier technique┘ (IEEE J. of Solid State Circuit, Vol. 11, pp. 374-378, 1976) by J. F. Dickson. However, they may suffer from many drawbacks, such as high instantaneous current, high supply voltage, or high threshold voltage shift due to the effects of the body.
For a single power supply system, the amplitude vibration of the clocks and the supply voltage is the same. To design a low-supply voltage, charge-pumping circuit generating a high output voltage, several stages of charge-pumping sub-circuits have to be connected in series.
FIG. 1
is an example of a four-stage positive charge-pumping circuit.
The circuit is a basic four-stage charge-pumping circuit. The charge-pumping circuit has five transistors being connected in series M
1
~M
5
; each gate is coupled to a drain and each substrate is coupled to a ground. The drain of transistor M
1
receives supply voltage (Vdd), and the drain of transistor M
5
supplies an output voltage (Vout). The four capacitors Cp
1
~Cp
4
are coupled to the drains of transistors M
2
~M
5
, respectively. In addition, there is a load capacitor (CL) coupled to Vout. Moreover, the other sides of Cp
1
~Cp
4
are interlacedly coupled to clock (&phgr;) or the inverted signal ({overscore (&phgr;)}). As the stages progress, the body effects become more severe near the output node Vout, and thus it is difficult for Vout to pump up to a higher positive voltage. For the P-Well process with N-Type substrate technologies, since a N-MOSFET can be isolated from others using different P-Wells, the substrate electrode of N-MOSFET can be coupled to the gate and drain electrodes. The MOS transistors become diodes. The body effect disappears, but the circuit may be damaged due to the high instantaneous current due to diode conduction. For the
N-Well process with P-Type substrate technologies, P-MOSFET's can be used to build the pumping circuit employing the similar approach, but the same problem may occur.
SUMMARY OF THE INVENTION
The present invention proposes an improved charge-pumping circuit based on Dickson charge-pumping circuit. The improvement can be utilized under low-supply voltage conditions to generate high positive or negative voltage, to enhance charge transfer efficiency, to eliminate the body effects and high instantaneous current, and to resolve the problems of reverse charge-sharing.
The present invention proposes a charge-pumping circuit, and includes a plurality of first, second and third transistor groups and a secondary charge-pumping circuit for supplying low supply voltages. Herein, the source of each transistor of the first transistor group is coupled to the drain of the successive transistor so that all transistors of the first transistor group are coupled in series. The drain of the first transistor of the first transistor group is coupled to the supply voltages. The source of the last transistor of the first transistor group is coupled to the output of the pumping circuit, and the gate of the last transistor of the first transistor group is coupled to its own drain. Each transistor of the second transistor group has a corresponding transistor of the first transistor group exclusively, except the first and the last transistor of the first transistor group. The drain of each transistor of the second transistor group is coupled to its own gate, and to the gate of the corresponding transistor of the first transistor group. The source of each transistor of the second transistor group is coupled to its own p-well, and to the drain of its corresponding transistor of the first transistor group. Moreover, each transistor of the third transistor group has a corresponding transistor of the first transistor group exclusively. The p-well of each transistor of the third transistor group is coupled to its own source, and to the p-well of its corresponding transistor of the first transistor group. The drain of each transistor of the third transistor group is coupled to the source of its corresponding transistor of the first transistor group. The gate of the first transistor of the third transistor group corresponding to the first transistor of the first transistor group is coupled to the clock. Excluding the first transistor of the third transistor group, the gate of each transistor of the third transistor group is coupled to the drain of the corresponding transistor of the first transistor group. Each capacitor of a first capacitor group has a corresponding transistor of the first transistor group excluding the first transistor. The first end of each capacitor of the first capacitor group is coupled to the drain of its corresponding transistor of the first transistor group; the second end of each capacitor of the first capacitor group is interlacedly coupled to the clock or the inverted signal.
The secondary charge-pumping circuit mentioned above includes a plurality of fourth and fifth transistor groups and a second capacitor group. Therefore, the source of each transistor of the fourth transistor group is coupled to the drain of successive transistors so that all transistors of the fourth transistor group are coupled in series. The drain of the first transistor of the fourth transistor group is coupled to the supply voltage. The source of the last transistor of the fourth transistor group is coupled to the output of the pumping circuit, and the gate of the last transistor of the fourth transistor group is coupled to its drain. Each transistor of the first transistor group has a corresponding transistor of the fourth transistor group exclusively, except for the first and the second transistors of the fourth transistor group; and the gate of each transistor of the first transistor group is coupled to the corresponding gate of each transistor of the fourth transistor group. Each transistor of the fifth transistor has a corresponding transistor of the fourth transistor group. Moreover, p-well of each transistor of the fifth transistor group is coupled to its own source, and to the p-well of the corresponding transistor of the fourth transistor group. The drain of each transistor of the fifth transistor group is coupled to the source of the corresponding transistor of the fourth transistor group. The gate of the first transistor of the fifth transistor group corresponding to the first transistor of the fourth transistor group is coupled to the clock. The gates of other transistors of the fifth transistor group are coupled to the drains of the corresponding transistors of the fourth transistor group. Each capacitor of the second capacitor group has a corresponding transistor of the fourth transistor group excluding the first transistor. The first end of each capacitor of the second capacitor group is coupled to the drain of the corresponding transistor of the fourth transistor group; the second end of each capacitor of the second capacitor group is interlacedly coupled to the clock or the inverted signal.
The present invention eliminates the body effect due to the third transistor group added, and eliminates the reverse charge-sharing problems due to the second transistor group added. Thus,

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