Electric power conversion systems – Current conversion – With voltage multiplication means
Reexamination Certificate
2000-01-19
2001-02-20
Wong, Peter S. (Department: 2838)
Electric power conversion systems
Current conversion
With voltage multiplication means
C307S111000, C307S328000, C307S402000
Reexamination Certificate
active
06191963
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to charge pumps used to generate voltage having a greater magnitude than the positive and negative power supply rails, and, in particular, to positive charge pumps that generate an output voltage higher than the power supply and to negative charge pumps that generate an output voltage lower than ground or the negative supply voltage.
2. Description of the Related Art
It is useful to be able to generate a voltage greater in magnitude than the maximum supply voltages available in a given circuit or system. Charge pumps are often used for this purpose, to convert a low magnitude voltage to a higher magnitude voltage (whether negative or positive). For example, charge pumps are employed in various types of circuits, such as integrated circuits (ICs), to generate an output voltage higher than the power supply (e.g., V
DD
) or lower than ground or the negative supply voltage (e.g., V
SS
). These are known as positive and negative charge pumps, respectively. Both types of charge pumps generate an output voltage having a greater magnitude than the magnitude of either the positive or negative power supply voltages (V
DD
and V
SS
or ground).
Charge pumps typically operate by using a chain of switches to transfer cumulatively increasing charges from one capacitively boosted node to the next. These switches typically comprise a series of clocked diode-capacitor voltage multiplier circuits. By using such charge-coupling techniques, the voltage is lowered (for a negative charge pump) or raised (for a positive charge pump) in incremental steps from one stage to the next. Thus, at each stage, the cumulative voltage increases in magnitude, until a final stage, at which point the output voltage is to be applied to a given load.
After the final stage of the charge pump, a diode switch is typically used to transfer the cumulated charge to the load. The diode switch also prevents charge from feeding back from the load into the charge pump, which would otherwise reduce the pumping action and thus reduce the magnitude of the charge pump's output voltage applied to the load. Unfortunately, however, due to the forward diode voltage (up to 3V, depending upon the design) drop across the diode, the magnitude of the ultimate charge pump output voltage applied to the load is less than the last stage voltage at the input of the diode switch.
This can reduce the efficacy of the charge pump. For example, one technique for erasing Flash EEPROM memory cells involves applying or “steering” a negative erasure voltage to all of the rows of the memory array. This negative erasure voltage must be isolated from the rows at other times so that the memory cells are not continually erased. However, when using a typical conventional charge pump for such Flash EEPROM erasure purposes, the magnitude of the negative voltage reaching each row is reduced by one p-channel threshold (about 1V), due to the use of the diode switch coupled to the last internal stage or node of the charge pump.
One prior art charge pump is the positive charge pump circuit described in Jieh-Tsorng Wu & Kuen-Long Chang, “MOS Charge Pumps for Low-Voltage Operation,”
IEEE J. Solid
-
State Circuits
, vol. 33, no. 4 (April 1998), pp. 592-597, the entirety of which is incorporated herein by reference. Other prior art charge pumps are disclosed in U.S. Pat. No. 5,907,484, issued to Kowshik et al., and in U.S. Pat. No. 5,912,560, issued to Pasternak. The Wu & Chang positive charge pump is represented by charge pump circuit
100
of FIG.
1
. Prior art charge pump
100
is based on a four-stage Dickson charge pump, which uses a two-phase nonoverlapping clock (PHI
1
and complementary clock PHI
2
), and a series of MOS capacitor switches and capacitors to couple subsequent nodes or stages to higher and higher cumulative voltages. Charge pump
100
comprises four stages, each coupled at an output node to one of four nodes N
1
, N
2
, N
3
, N
4
. The input of the first stage is coupled to input voltage, i.e. V
DD
. The output at each succeeding stage, e.g. voltage V
1
at node N
1
, is cumulatively higher, when charge is gated or pumped through the chain of stages, by the operation of clock signals PHI
1
, PHI
2
, applied to stages via coupling or boost capacitors MC
1
, MC
2
, MC
3
, MC
4
. Illustrative clock phases for clock signals PHI
1
, PHI
2
, are shown in FIG.
2
.
Each stage of the charge pump has a diode-connected MOS transistor MDi, so that the charges can be pushed in only one direction. The two pumping clocks PHI
1
, PHI
2
are out of phase and have a voltage amplitude of V
PHI
, which is usually identical to the supply voltage V
DD
. Through the coupling or boost capacitors MC
1
, MC
2
, MC
3
, MC
4
, the two clock signals push the charge voltage upward through the transistors.
The internal most positively charged pump node, N
4
, has the charge pump voltage V
C
, which needs to be gated to the load (load resistance R
L
in parallel with load capacitance C
L
). The output node OUT, at output voltage V
O
, is coupled to node N
4
by a diode-switch MS
5
, which is a MOS transistor connected in a diode configuration, i.e. with its gate G connected to its drain D. This allows positive charge to flow out of the charge pump and into the load, but prevents positive charge from flowing back into the pump when node N
4
is coupled low, through capacitor MC
4
, by clock PHI
2
being driven low. The output voltage V
O
of a charge pump circuit is a function of the input power supply, the number of pump stages, the clock frequency, and the load current at the output terminal.
A disadvantage resulting from use of diode switch MS
5
is that the maximum theoretical output voltage OUT is one high back-gate biased n-channel threshold (Vt, e.g. 2V) below the voltage of N
4
, when it has just been coupled high via capacitor MC
4
driven by clock PHI
2
going high. Thus, because of the threshold voltage drop across diode switch MS
5
, the actual output voltage V
O
is less than V
O
e.g. by about 2V. As is well known, threshold voltage increases with increasing source to back-gate bias, V
sb
. Thus if the back-gate connection of MS
5
is at ground, a typical condition, the threshold voltage of MS
5
increases significantly as the charge pump's output, which is the source voltage on MS
5
, is pumped high. For example, if MS
5
had a threshold voltage of 0.7 volts when V
sb
is 0 volts, then typically the threshold voltage might increase to 2 volts when to charge pump's output, and therefore V
sb
is pumped up to 8 volts.
The positive charge pump described in the Wu & Chang reference can be reconfigured as a negative charge pump by replacing the n-channel devices thereof with p-channel devices, inverting the clocks PHI
1
and PHI
2
, and changing the power input from V
DD
to ground. In such a negative charge pump, the output voltage again has a smaller (negative) magnitude than at the preceding stage N
4
, due to the voltage drop across the diode switch. Accordingly, there is a need for improved charge pumps.
SUMMARY
An integrated circuit-based charge pump generates an output voltage having a greater magnitude than a power supply voltage. The charge pump has a charge pump section having a plurality of alternating stages driven by first and second alternating, non-overlapping clock signals, said plurality of alternating stages including an input stage for receiving the power supply voltage and an output stage for generating at a last stage node a last stage voltage having a greater magnitude than the power supply voltage. A gating transistor is coupled at a drain terminal to the last stage node, wherein the gating transistor is clocked by one of said clock signals and is biased so that the gating transistor, during a boost phase, gates the last stage voltage to a load coupled to the source terminal of the gating transistor without a voltage drop and, at other times, turns off to prevent charge from flowing from the load into the last stage node of the charge pump sect
Banerjee Amit Kumar
Loeper Duane J.
McPartland Richard Joseph
Duane Morris & Heckscher LLP
Laxton Gary L.
Lucent Technologies - Inc.
Wong Peter S.
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