Charge pump with four-well transistors

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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C327S536000, C257S499000

Reexamination Certificate

active

07466190

ABSTRACT:
In one embodiment, a (negative-voltage) charge pump with one or more stages that receives a (high) input voltage and generates a higher-magnitude (negative) output voltage. Each stage has two capacitors for storing charges and two branches that alternate to transmit a higher-magnitude output voltage at every clock half cycle. Each branch has a PMOS transistor and a NMOS transistor. To reduce the effects of back body from the substrate, two transistors are constructed with three wells and two with four wells, where the number of wells per device is dependent upon the substrate type used.

REFERENCES:
patent: 6100557 (2000-08-01), Hung et al.
patent: 6496055 (2002-12-01), Li
patent: 6750527 (2004-06-01), Momohara
patent: 6777978 (2004-08-01), Hart et al.
patent: 6819162 (2004-11-01), Pelliconi
patent: 7009857 (2006-03-01), Chen et al.
patent: 7089527 (2006-08-01), Hart et al.
patent: 2003/0214346 (2003-11-01), Pelliconi
“Power Efficient Charge Pump in Deep Submicron Standard CMOS Technology,” by Roberto Pelliconi et al., Proceedings of the 27thEuropean Solid-State Circuits Conference, Sep. 18-20, 2001, 4 pages.

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