Charge pump with efficient switching techniques

Details Charge pump with efficient switching techniques Charge pump with efficient switching techniques

2000-12-11

2002-03-19

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

06359500

ABSTRACT:

TECHNICAL FIELD
This invention relates to the field of charge pumps in semiconductor electrical devices, and, more specifically, to methods of driving new and existing charge pumps in such a way as to increase their overall efficiency.
BACKGROUND OF THE INVENTION
Non-volatile memories (NVMs) that are only supplied with a single voltage (Vdd) generally include both positive and negative voltage boost circuits in order to produce necessary on-chip voltages that are different from the Vdd supply. NVMs require high voltages to program and delete information stored in the individual memory cells.
The contribution to the total power dissipation of the chip of these voltage boost circuits is usually high, sometimes up to 30% of the total power dissipated by the chip. Additionally, such components of the system are further characterized by very low yields, typically around 30%. The problem is particularly relevant to the application fields of NVMs—and, more in general, to the chips having internal DC/DC up converters (charge pumps) in which the power at disposal of the system supply is limited and expensive.
Important examples include portable devices such as cellular phones, palmtops, notebooks, smart cards, movable equipment, communication apparatuses, biomedical apparatuses, digital cameras, MP3 players, etc. Such applications generally require a battery, presenting cost, duration, weight and dimension issues that can be made less onerous by particularly modifying the power requirements of the system they have to supply.
Such applications also generally utilize NVMs, particularly FLASH memories, and power converters. Thus, one way to reduce power consumption in these devices is to reduce the power used by charge pumps, which are some of the main agents responsible for the power dissipation in these low-power systems.
The prior art includes charge pumps, or voltage boosters, that are formed in CMOS technology and include both P and N type transistors. A booster is formed by a series of (n) stages, each including a high value boosting capacity (typically a capacitor) and a switch that allows a current to flow. In the case of positive charge pumps, the current flows from the Vdd supply to the output node. An example of such a positive boost circuit is shown in FIG.
1
.
In positive charge pumps, the number of separate stages (n) is a function of the Vdd supply voltage and the desired output voltage. Particularly, the asymptotic value of the output voltage is given by V
out
=(n+1l)V
dd
.
In general, as shown in
FIG. 2
, a typical charge pump
5
receives a voltage signal Vin, and, through the driving signals A, B, C and D, produces an output voltage signal Vout, which is coupled to an output capacitance. The driving signals are provided by a phase driver
8
.
One of the best present architectures from the efficiency and performance standpoint is the one in which the k-nth elementary stage is a circuit as that shown in FIG.
3
. In that Figure, a multi-stage circuit
10
includes an NMOS transistor type switch
20
coupling an end-stage node
28
to an inter-stage node
25
. Another NMOS transistor switch gate
24
used for separating two adjacent stages is also shown. Boost capacitances
22
are comparable with the load capacitance Cload of FIG.
2
.
A respective timing diagram showing operation of the circuit shown in
FIG. 2
is indicated in FIG.
4
. In
FIG. 4
the signals associated with the labels A, B, C, and D denote voltage signals applied to the respective nodes in FIG.
2
. Note that node A is not shown in
FIG. 3
, but would reside before node B, and be structured like the node C. The signals B and D are boost phases and phases A and C are used to boost the switch
24
at high voltage.
When B goes HIGH at a time T
0
, the transistor
20
is ON and a node
25
charges toward potential of the node
28
through the transistor
20
. Once charged, the node
25
stays isolated since D goes LOW shortly (Dt time after T
0
) after B goes HIGH, thus turning off the transistor
20
. Driving the node C causes a mini-boost effect on the transistor
24
, through a driving capacitor
26
. The driving capacitor
26
generally has a capacitance value of about one order lower than that of the boost capacitors
22
. In this way, the NMOS conductivity of transistor
24
stays high, and since the transistor
20
turns OFF only when D goes low, the charge packet transfer from one stage to another occurs only in the direction toward an output node at the last stage (not shown in FIG.
3
), and not vice-versa. As seen in
FIG. 4
, when D goes HIGH, also C switches LOW, turning OFF the transistor
24
in FIG.
3
. This process is repeated for the number of stages downstream toward the output node. At each process, the transistor switches
20
,
24
alternatively open and close. If the transistor switches
24
having even number k's are open, then the even numbered transistors
20
will be closed and vice versa, depending on the timing of the phases.
A known realization
30
in the art of boost drivers for the charge pumps is shown in FIG.
5
. Boost drivers are widely used and are the main dissipation sources inside a charge pump. In this Figure, the boost drivers include triple-state buffers
32
and
34
. In the operation of this circuit
30
, the switching of the boost phases B and D (
FIG. 4
) is preceded by an equalization operation between output nodes of the drivers
32
,
34
, implemented by turning on an equalizing transistor
36
. In doing so, charge sharing occurs between nodes F and G, respectively located at the output nodes of the drivers
32
,
34
, while the drivers
32
,
34
present a high impedance level. Without regarding parasitic capacitances, the nodes F and G obtain a midpoint at a voltage about Vdd/2. At the end of the charge sharing operation, the two drivers
32
,
34
, lose their high impedance level and switch.
This charge sharing function allows an energy sharing at a driver level theoretically equal to 50%, but actually it is limited to the unavoidable change of the timing pulses. The physical implementation of the wave forms shown in
FIG. 4
will not be exactly as shown in that Figure, but rather will have imperfections. In fact, if the nodes F and G simultaneously switch because of the equalization through the transistor
36
, and supposing that B has to go HIGH and D LOW, the transistor switch
20
switches OFF prematurely. This premature shutoff prevents the node
25
from reaching the optimal voltage value to be able to easily drive the transistor
24
.
Another problem exists when driving charge pumps, such as the charge pump shown in FIG.
3
. In operation, the transistors of the charge pump are affected by the well known Body effect, due to the large potential difference between the switch well and the source junction. This effect is particularly pronounced in stages that are close to the output. When this effect is pronounced, the threshold voltages increase too much and the transistor conductivity is “penalized” because it depends on the decrease of the voltage Vgs−Vt. Furthermore, the drain and source roles change during the actual boost phases, and this involves great difficulties to reduce the body effect. Also, the lessened conductivity involves the lowered threshold of the transistor and changes the output voltage from its normal asymptotic shape. Such limited conductivity further causes increased energy dissipation of the switch.
The problem of the body effect has been effectively solved by using NMOS transistors in a voltage divider and formed in a triple well implementation, as shown in FIG.
6
. In that Figure a circuit
40
is supplied by a pump output
42
, which is able to produce bias voltages of the wells for each stage, with the aim to reduce the potential difference between well and source and with the care of not having the well—drain and well—source junctions in direct conductivity.
Other solutions to reduce power dissipated by the charge pumps can, in general, intervene at a system level, particularly in NVMs. The

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