Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-02-16
2002-12-10
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
Reexamination Certificate
active
06492862
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a voltage conversion circuit, and more particularly to a charge pump type voltage conversion circuit which generates a boosted output voltage having reduced ripple voltage components.
BACKGROUND OF THE INVENTION
Conventional voltage conversion circuits are disclosed, for example, in Japanese patent laid-open publication No. 8-212781, Japanese patent laid-open publication No. 6-165482, Japanese patent laid-open publication No. 63-018958, Japanese patent laid-open publication No. 63-018959, Japanese patent laid-open publication No. 5-276737, and the like.
The voltage conversion circuits described in these publications are used for obtaining a positive or negative output voltage which has a larger magnitude than that of a power supply voltage, from a single power supply voltage. Otherwise, the voltage conversion circuits described in these publications are used for obtaining an output voltage which has a smaller magnitude than that of a power supply voltage, from a single power supply voltage.
In order to compose such voltage conversion circuit on a printed circuit board, there is used a three terminal-type voltage regulator, a switching regulator which uses a coil component, or the like. However, the three terminal-type voltage regulator has a disadvantage that a power loss by a transistor of an output circuit stage thereof becomes large. Also, although a power loss of the switching regulator is relatively smaller than that of the three terminal-type voltage regulator, the switching regulator has a disadvantage that the size of the device becomes large because it uses a coil component.
In order to avoid the above-mentioned disadvantages, when, for example, a voltage conversion circuit is to be formed on an semiconductor integrated circuit device, a charge pump-type voltage conversion circuit is used. The charge pump-type voltage conversion circuit has the merits of low power loss, good compatibility with a semiconductor integrated circuit in a manufacturing process thereof, and the like.
As an example, a voltage conversion circuit outputting a positive voltage is used in a power supply circuit portion in an integrated circuit of an RS-232C (interface standard) driver/receiver, and the like. Also, a voltage conversion circuit outputting a negative voltage is used in a power supply circuit for a negative voltage source of an operational amplifier or a comparator, and the like.
Each of these voltage conversion circuits has a voltage conversion portion composed of a switched capacitor circuit which comprises switches and capacitors and which operates based on a clock signal supplied from a clock generator portion.
As another example, in Japanese patent laid-open publication No. 11-187545, there is disclosed a circuit structure which has a function of enabling or disabling a voltage raising operation, depending on whether or not a voltage corresponding to the difference between an output of a charge pump and a power supply voltage exceeds a reference voltage.
However, in such circuit structure, when a load is connected to an output terminal thereof, a relatively large voltage ripple arises at the output terminal due to the influence by the electric charges consumed by the load, and it is impossible to make an influence of such voltage ripple small.
With reference to the drawing, an explanation will be made on a practical example of a conventional voltage conversion circuit.
FIG. 5
is a circuit diagram illustrating an example of a conventional voltage conversion circuit. As shown in
FIG. 5
, the voltage conversion circuit includes a voltage detector circuit
1
, a clock oscillator circuit
2
a
, a latch circuit
3
, a charge pump circuit
4
a
, and a compensation capacitor CL. The voltage detector circuit
1
is a circuit which compares a divided output voltage VO
2
of a boosted voltage output VO
1
with a reference voltage VR
1
, and outputs a voltage detection signal &phgr;
1
depending on the result of the comparison. The clock oscillator circuit
2
a
performs a controlled oscillation operation in response to the voltage detection signal &phgr;
1
, and outputs a clock signal &phgr;
2
. The latch circuit
3
latches the clock signal &phgr;
2
outputted from the clock oscillator circuit
2
in response to the voltage detection signal &phgr;
1
from the voltage detector circuit
1
. The charge pump circuit
4
a
charges capacitor elements C
1
and C
2
in response to the output signal of the latch circuit
3
, and produces the boosted voltage output VO
1
. The compensation capacitor CL is coupled between the output terminal and the ground.
Also, the voltage detector circuit
1
comprises a comparator
11
for comparing the reference voltage VR
1
and the divided voltage VO
2
of the boosted voltage output VO
1
, and resistors R
1
and R
2
for producing the divided voltage VO
2
. These resistors R
1
and R
2
are serially coupled between the boosted voltage output VO
1
and the ground, and the connection node between the resistor R
1
and the resistor R
2
is coupled with an inverting input (−side) of the comparator
11
. A non-inverting input (+side) of the comparator
11
is coupled with the reference voltage VR
1
. When the divided voltage VO
2
obtained by dividing the boosted voltage output VO
1
is lower than the reference voltage VR
1
, the voltage detection signal &phgr;
1
which is an output of the comparator
11
becomes logically high. On the other hand, when the divided voltage VO
2
is higher than the reference voltage VR
1
, the voltage detection signal &phgr;
1
becomes logically low.
The clock oscillator circuit
2
a
is basically composed of a ring oscillator comprising inverters I
2
-I
4
. An output of the inverter
14
of the final stage is fed back to an input of the inverter I
2
of the first stage, via a transfer gate TG
1
comprising an n-type MOS transistor and a p-type MOS transistor. Other inverters I
5
and I
6
designate output buffers for outputting the clock signal &phgr;
2
. TG
1
designates the transfer gate, Q
1
designates a MOS switch, I
1
designates an inverter for controlling the MOS switch Q
1
and the transfer gate TG
1
. Since there exist parasitic capacitances C
3
-C
5
at respective nodes in the ring oscillator having the above-mentioned structure, signal transition at each of the nodes becomes dull or blunted. Therefore, the clock oscillator circuit
2
a
requires buffering for wave shaping.
In the clock oscillator circuit
2
a
, the transfer gate TG
1
is on-off controlled by the voltage detection signal &phgr;
1
generated depending on the potential level of the boosted voltage output VO
1
. The transfer gate TG
1
becomes conductive only when the signal &phgr;
1
is logically high, and causes the ring oscillator circuit to oscillate and output the clock signal &phgr;
2
as an output thereof. On the other hand, when the voltage detection signal &phgr;
1
is logically low, an input node N
1
of the inverter
12
is clamped to low by the inverter I
1
and the transistor Q
1
, and fix the potential level of the clock signal &phgr;
2
to logically high. Generally, when an operation of a ring oscillator circuit is to be stopped, an input node is clamped to a low potential level or a high potential level, as in this circuit example, to avoid a floating condition of a potential level of each circuit node.
The latch circuit
3
has a transfer gate TG
2
composed of an n-type MOS transistor and a p-type MOS transistor, an inverter
114
, and clocked inverters
115
and
116
. The transfer gate TG
2
is controlled by the voltage detection signal &phgr;
1
from the voltage detector circuit
1
. When the voltage detection signal &phgr;
1
is in a high potential level, that is, when the divided voltage VO
2
produced from the boosted voltage output VO
1
is lower than the reference voltage VR
1
, the transfer gate TG
2
is turned on. When the voltage detection signal &phgr;
1
is in a low potential level, that is, when the divided voltage VO
2
produced from the boosted v
Michael Best & Friedrich LLC
Whitesel J. Warren
Zweizig Jeffrey
LandOfFree
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