Charge pump system for fast locking phase lock loop

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C327S157000

Reexamination Certificate

active

06897690

ABSTRACT:
A charge pump system for a fast locking phase lock loop includes a set n of charge pump units; and a control logic circuit for enabling the set of n charge pump units to produce up and down charge pulses with a nominal charge pump mismatch in a wide bandwidth mode; and in a narrow bandwidth mode enabling at least a subset of the n charge pump units sequentially to produce an average charge pump mismatch in narrow bandwidth mode that matches the nominal charge pump mismatch in the wide bandwidth mode.

REFERENCES:
patent: 4156855 (1979-05-01), Crowley
patent: 5889828 (1999-03-01), Miyashita et al.
patent: 6111470 (2000-08-01), Dufour
patent: 6230280 (2001-05-01), Okasaka
Rhee, W., “Design of High-Performance CMOS Charge Pums in Phase-Locked Loops”, IEEE International Symposium on Circuits and Systems (ISCAS), 1999, vol. 2, pp. 545-548.
“An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLL's”, National Semiconductor Application Note 1001, Jul. 2001, pp. 1-8.
Byrd, et al. “A Fast Locking Scheme for PLL Frequency Synthesizers”, National Semiconductor Application Note 1000, Jul. 1995, pp. 1-6.
Curtin et al. “Phase Locked Loops for High-Frequency Receivers and Transmitters-Part 3”, Analog Dialogue 33-7 (1999), pp. 1-5.
Rhee et al., “A 1.1-GHz CMOS Fractional-NFrequency Synthesizer with a 3-b Third-Order Delta Sigma Modulator”; IEEE Journal of Solid-State Circuits, vol. 35, No. 10, Oct. 2000, pp 1453-1460.
Greshishchev et al., “SiGe Clock and Data Recovery IC with Linear-Type PLL for 10-Gb/s SONET Application”; IEEE Journal of Solid-State Circuits, vol. 35, No. 9, Sep. 2000, pp 1353-1359.
Bastos et al., “A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC”; IEEE Journal of Solid-State Circuits, Vo. 33, No. 12, Dec. 1998, pp. 1959-1969.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Charge pump system for fast locking phase lock loop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Charge pump system for fast locking phase lock loop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Charge pump system for fast locking phase lock loop will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3441167

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.