Charge pump structure for reducing capacitance in loop...

Details Charge pump structure for reducing capacitance in loop... Charge pump structure for reducing capacitance in loop...

2002-11-07

2004-03-23

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S025000, C327S148000, C327S536000, C327S157000, C375S374000

Reexamination Certificate

active

06710666

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a charge pump of a phase locked loop, and more specifically, to an improved charge pump structure allowing for a smaller capacitor to be used in a loop filter of the phase locked loop.
2. Description of the Prior Art
A phase locked loop Is used for frequency control. Please refer to FIG.
1
.
FIG. 1
is a block diagram of a phase locked loop (PLL)
10
according to the prior art. The PLL
10
contains a phase detector
12
, which is used for comparing phases of two input signals IN
1
and IN
2
. Based on a phase difference between the two Input signals IN
1
and IN
2
, the phase detector
12
then outputs either an up signal UP or a down signal DN to a charge pump circuit
14
. Based on receipt of either the up signal UP or the down signal DN, the charge pump circuit
14
sends (or receives) a control current to (from) a loop filter
16
. This control current is used for charging or discharging a capacitor within the loop filter
16
, as will be explained more thoroughly below. Finally, a control voltage V
VCONA
is outputted from the loop filter
16
and fedg Into a voltage controlled oscillator (VCO)
18
. The VCO
18
generates the output frequency IN
2
based on the control voltage V
VCONA
that is fed into the VCO
18
. Together, the phase detector
12
, the charge pump circuit
14
the loop filter
16
, and the VCO
18
form the PLL
10
, which is a negative feedback loop.
Please refer to FIG.
2
.
FIG. 2
is a diagram illustrating operation of the phase detector
12
of the PLL
10
when generating the up signal UP. As stated above. the phase detector
12
compares two inputted signals IN
1
and IN
2
, and outputs either the up signal UP or the down signal DN based on the phase difference between IN
1
and IN
2
. In
FIG. 2
the IN
1
signal leads the IN
2
signal by a phase difference of &thgr;
1
. The phase detector
12
is able to detect this phase difference and then outputs a pulse of the up signal UP. A pulse width of the up signal UP is directly proportional to the phase difference &thgr;
1
between IN
1
and IN
2
. This up signal UP is ultimately used to increase the frequency of IN
2
so that IN
1
and IN
2
can become in-phase.
Please refer to FIG.
3
.
FIG. 3
is a diagram illustrating operation of the phase detector
12
of the PLL
10
when generating the down signal DN. In
FIG. 3
, the IN
2
signal leads the IN
1
signal by a phase difference of &thgr;
2
. The phase detector
12
is able to detect this phase difference and then outputs a pulse of the down signal DN. A pulse width of the down signal DN is directly proportional to the phase difference &thgr;
2
between IN
1
IN
2
. This down signal DN is ultimately used to decrease the frequency of IN
2
so that IN
1
and IN
2
can become in-phase.
Please refer to FIG.
4
.
FIG. 4
is a circuit diagram of the charge pump circuit
14
and the loop filter
16
of the prior art. The charge pump circuit
14
comprises an input current source
20
, which is connected to node NA of the charge pump circuit
14
that inputs a current with a magnitude of I, and an output current source
22
, which Is connected to node NB of the charge pump circuit
14
, that outputs a current with a magnitude of I. The charge pump circuit
14
further comprises an up.pulse switch swUP connected between node NA and output node VCONA, and a down pulse switch swDN connected between node VCONA and node NB. The loop filter
16
comprises a resistor R connected between the output node VCONA and an intermediate node VCON, and a capacitor C connected between the intermediate node VCON and ground.
When a pulse of the up signal UP is received from the phase detector
12
, the up pulse switch swUP is programmed to close for charging the capacitor C. At all other times, the up pulse switch swUP remains open. On the other hand, when a pulse of down signal DN is received from the phase detector
12
, the down pulse switch swDN is programmed to close for discharging the capacitor C. At all other times, the down pulse switch swDN remains open. As shown in
FIG. 4
, both the up pulse switch swUP and the down pulse switch swDN are shown open since neither the up signal UP nor the down signal DN are received by the charge pump circuit
14
. Therefore, no current is able to flow from the charge pump circuit
14
to the loop filter
16
in order to charge or discharge the capacitor C.
Please refer to FIG.
5
.
FIG. 5
is a circuit diagram of the prior art charge pump circuit
14
and loop filter
16
in a charging mode. In
FIG. 5
, the charge pump circuit
14
receives a pulse of the up signal UP from the phase detector
12
. Therefore, the up pulse switch swUP is closed and the down pulse switch swDN is open. A dotted line is shown illustrating a path of current with the magnitude of I from the input current source
20
through the resistor R and through the capacitor C. Since the current I is flowing through the capacitor C, the voltage across the terminals of the capacitor C will increase, and the capacitor C will be charged according to Eqn.1 shown below.
i
=
C
⁢
 
⁢
ⅆ
v
ⅆ
t
(
1
)
Eqn.1 shows that the longer the current I is flowing through the capacitor C, the more charged the capacitor C will become, and the larger a voltage V
VCON
will be. From Eqn.1, a simple proportionality relationship can be made, which is shown in Eqn.2.
i
k
=
C
k
(
2
)
In Eqn.2, k is a constant. The present invention makes great use of Eqn.2 and the significance of this equation will be explained fully below. As mentioned above, the voltage V
VCONA
is an output voltage that it outputted from the loop filter
16
to the VCO
18
for controlling the VCO
18
. Eqn.3 below shows the relationship between the voltage V
VCONA
and the voltage V
VCON
.
V
VCONA
−IR+V
VCON
  (3)
Eqn.3 shows that the voltage V
VCONA
depends on the sum of the current I flowing through resistor R and the voltage V
VCON
.
Please refer to FIG.
6
.
FIG. 6
is a circuit diagram of the prior art charge pump circuit
14
and loop filter
16
in a discharging mode. In
FIG. 6
, the charge pump circuit
14
receives a pulse of the down signal DN from the phase detector
12
. Therefore, the down pulse switch swDN is closed and the up pulse switch swUP is open. A dotted line is shown illustrating a path of current with the magnitude of I from the capacitor C through the resistor R to the output current source
22
. Since the current I is leaving the capacitor C, the voltage across the terminals of the capacitor C will decrease, and the capacitor C will be discharged according to Eqn.1.
Unfortunately, when fabricating the prior art charge pump circuit
14
and loop filter
16
on an Integrated circuit (IC), the area of the capacitor C takes up a very large area of the IC. Not only does this increase the cost to manufacture the ICs containing the prior art PLL
10
, but it also makes it difficult to design and build smaller ICs due to the large size of the capacitor C.
SUMMARY OF INVENTION
It is therefore a primary objective of the claimed invention to provide a charge pump circuit for reducing capacitance in a loop filter of a phase locked loop in order to solve the above-mentioned problems.
According to the claimed invention, a charge pump circuit is used for reducing capacitance in a loop filter of a phase locked loop. The loop filter contains a resistor electrically connected to the charge pump circuit at an output node and a capacitor being electrically connected to the resistor at an intermediate node. The charge pump circuit contains a first input current source electrically connected to a first node of the charge pump circuit for supplying a first current to the charge pump circuit, the first current being equal to a predetermined amount of current multiplied by a first factor, and a second input current source electrically connected to a second node of the charge pump circuit for supplying a second current to the charge pump circuit, the second current being equal to the pr

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