Charge pump stage with body effect minimization

Details Charge pump stage with body effect minimization Charge pump stage with body effect minimization

2001-04-05

2004-01-13

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S537000, C363S060000

Reexamination Certificate

active

06677805

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to charge pumps for boosting voltages in microelectronic circuitry, and particularly to a charge pump stage architecture with body effect minimization.
BACKGROUND OF THE INVENTION
Non-volatile memory arrays, such as erasable, programmable read only memory (EPROM) or flash memory arrays, or electrically erasable, programmable read only memory (EEPROM) arrays, require high positive or negative voltages to program and erase memory cells of the array. Typically, these voltages are higher than the voltage supplied (V
dd
). Charge pumps are generally used to boost on-chip voltages above the supply voltage V
dd
to reach the voltages required for program or erasing.
A charge pump typically comprises cascaded stages that progressively boost the voltage to higher levels. The charge pump functions by progressively storing more charge on a capacitor which is part of a capacitor-diode combination, with several such stages being placed together in a network to obtain the desired increase in voltage. The diode functions to prevent discharge of the capacitor prior to placing the additional charge thereon.
Reference is now made to
FIGS. 1A and 1B
, which illustrate a commonly used charge pump architecture, called a four-phased-clock, threshold-voltage-canceling pump architecture, for a four-stage charge pump (see Umezawa, IEEE Journal of Solid State Circuits Vol. 27, 1992, page 1540).
FIG. 1A
illustrates two stages of the charge pump in greater detail than
FIG. 1B
, which illustrates four stages of the charge pump.
The charge pump circuit includes a plurality of charge transfer transistors (reference letters m
1
) connected in series. In
FIG. 1B
, four such charge transfer transistors are shown, labeled m
1
, m
2
, m
3
and m
4
. Charge transfer transistors m
1
may use, but are not limited to, CMOS (complementary metal oxide semiconductor) technology, being either n-channel or p-channel (NMOS or PMOS) field effect transistors (FETs). (As explained further hereinbelow, NMOS is generally used to pump positive voltages, whereas PMOS is generally used to pump negative voltages.) The MOSFETs have a control electrode (gate, labeled g), a first electrode (drain, labeled d) and a second electrode (source, labeled s), connected to nodes, as described hereinbelow. (Since MOSFETs are typically symmetrical components, the true designation of “source” and “drain” is only possible once a voltage is impressed on the terminals of the transistors. The designations of source and drain throughout the specification should be interpreted, therefore, in the broadest sense.) Preferably, the bulks (labeled b) of the charge transfer transistors m
1
are coupled to a reference line (shown as REF in
FIG. 1A
, but omitted for the sake of simplicity in
FIG. 1B
) for receiving a reference voltage, generally ground in the case of NMOS.
FIGS. 1A and 1B
illustrate a positive charge pump based on NMOS. The source of charge transfer transistor m
1
is connected to node n
0
, which is connected to V
dd
. The gate of charge transfer transistor m
1
is connected to node g
1
, and the drain is connected to node n
1
. The source of charge transfer transistor m
2
is connected to node n
1
, the gate is connected to node g
2
, and the drain is connected to node n
2
. Similarly, as shown in
FIG. 1B
, the source of charge transfer transistor m
3
is connected to node n
2
, the gate to node g
3
, and the drain to node n
3
. Likewise, the source of charge transfer transistor m
4
is connected to node n
3
, the gate to node g
4
, and the drain to nodes.
Two-phase, non-overlapping pulse trains PH
1
and PH
2
are provided, such as from a pulse generator (not shown). By non-overlapping it is meant that 0 to 1, and 1 to 0 voltage transitions of one pulse never overlap with the transitions of the other pulse. The PH
1
and PH
2
phases inject energy into the pump through large capacitors
5
into nodes n
i
. Accordingly, in the illustrated embodiment, a large capacitor
5
is connected from pulse train PH
1
to node n
1
, and another large capacitor
5
is connected from pulse train PH
1
to node n
3
. Another large capacitor
5
is connected from pulse train PH
2
to node n
2
, and another large capacitor
5
is corrected from pulse train PH
2
to node n
4
. The charge is transferred along the pump through charge transfer transistors m
i
connecting node n
1
to node n
1+l
.
Similarly, two-phase, non-overlapping pulse trains PH
1A
and PH
2A
are also provided. The PH
1A
and PH
2A
phases inject energy into the pump through small capacitors
11
into nodes g
i
. Capacitors
11
preferably have a much smaller capacitance than large capacitors
5
. In the illustrated embodiment, a small capacitor
11
is connected from pulse train PH
1A
to node g
2
, and another small capacitor
11
is connected from pulse train PH
1A
to node g
4
. Another small capacitor
11
is connected from pulse train PH
2A
to node g
1
, and another small capacitor
11
is connected from pulse train PH
2A
to node g
3
.
As seen in
FIGS. 1A and 1B
, a plurality of auxiliary transistors t
1
(ie., t
1
, t
2
, t
3
and t
4
) are provided. Each auxiliary transistor t
1
has its drain connected to the gate node g
1
of each charge transfer transistor m
i
(i.e. m
1
, m
2
, m
3
and m
4
, respectively). The source of each auxiliary transistor t
i
is connected to the source of each charge transfer transistor m
1
(i.e., node n
i−1
). The gate of each auxiliary transistor t
i
is connected to the drain of each charge transfer transistor m
i
(i.e., node n
i
) The bulk of each auxiliary transistor t
i
is connected to the bulk of each charge transfer transistor m
i
, which is generally grounded. The auxiliary transistors t
i
and the PH
1A
and PH
2A
phases control the gate voltage of the charge transfer transistors m
i
.
The operation of the first stage of the pump is now explained, with all subsequent stages operating in the same manner. The operation commences with the PH
1
phase starting to rise. Initially, charge transfer transistors m
1
and m
2
are non-conducting (i.e., turned off), since the PH
1A
and PH
2A
phases are in their low phase. The PH
1
phase then fully rises and injects energy into node n
1
, raising (or “pushing”) node n
1
to a voltage boosted above V
dd
, such as 2 V
dd
. The rise of node n
1
forces node g
1
to V
dd
through auxiliary transistor t
1
. Since the source of charge transfer transistor m
1
is connected to V
dd
at node n
0
, the gate-source voltage bias V
gs
of charge transfer transistor m
1
is zero, assuring that transistor m
1
is turned off.
After a short time, typically in the order of several nanoseconds, the PH
1A
phase rises, which makes charge transfer transistor m
2
conduct (i.e., turns on). During this the, node n
1
is at a higher voltage than node n
2
. Since, as just mentioned, charge transfer transistor m
2
is conducting, charge is transferred from node n
1
to node n
2
. During the next phase, the PH
2
phase rises and the PH
1
phase drops. This causes node n
1
to drop and node n
2
to rise, thereby causing charge to be transferred from node n
2
to node n
3
. In this manner charge is transferred along the pump. Each of the g
i
nodes is raised by a V
dd
level with respect to the n
i
nodes when charge transfer is taking place. In the latter stages of the pump, the source and drain nodes (i.e., nodes n
3
and n
4
) are raised well above the bulk, which is usually grounded.
The large voltage difference between the high source/drain voltages and the low bulk voltage causes a problem, called the body or bulk effect, which is now explained. (The terms body and bulk are used interchangeably throughout the specification and claims)
Positive charge pumps generally use NMOS transistors, and this requires the body of the charge transfer transistors to be at the lowest voltage, in general ground (GND). (Negative charge pumps have the opposite requirement, and PMOS transistors are generally used.) However, in positive charge pumps there

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