Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2002-07-17
2003-08-19
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S536000, C331S00100A, C363S059000, C363S060000
Reexamination Certificate
active
06608511
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a phase-locked loop (hereinafter referred to as PLL) circuit. More particularly, the invention relates to a charge-pump PLL circuit with charge calibration.
2. Description of the Related Art
Many electronic and computer systems and components have critical timing requirements that compel generation of periodic clock waveforms that are precisely synchronized with a reference clock waveform. A phase-locked loop (PLL) is one type of circuit that is widely used to provide an output signal having a precisely controlled frequency that is synchronized with the frequency of a received or input signal. Frequency synthesizers, multipliers and dividers, single and multiple clock generators, clock recovery circuits, and wireless communication devices are (but a few) examples of the manifold implementations of PLLs.
FIG. 1
illustrates a block diagram of a typical charge-pump PLL
100
. The charge-pump PLL circuit
100
includes a phase detector
110
, a charge pump circuit
120
, a loop filter
130
, a voltage-controlled oscillator (VCO)
140
and a frequency divider
150
. The PLL
100
receives a reference clock signal CLK
ref
having a frequency F
ref
and generates an output clock signal CLK
out
having a frequency F
out
that is synchronized with the reference clock signal CLK
ref
in phase. The reference clock signal CLK
ref
is coupled into the phase detector
110
, where it is compared with a feedback signal CLK′
out
. Based on this comparison, the phase detector
110
generates a pump-up signal UP and a pump-down signal DN which, in turn, direct the charge pump circuit
120
to either source or sink current to or from the loop filter
130
which develops a voltage V
c
for adjusting the output frequency of the VCO
140
. The output of the VCO
140
, which is the output of the PLL
100
, is coupled to the frequency divider
150
. The feedback signal CLK′
out
may be the same as the output clock signal CLK
out
from the VCO
140
, or as illustrated in
FIG. 1
the feedback signal CLK′
out
may be the output of the frequency divider
150
. Although the frequency divider
150
is commonly used in the PLL
100
to divide the frequency received from the VCO
140
by N, it may be eliminated in certain applications.
The charge pump
120
generates a current I
CP
that develops the voltage V
c
across the loop filter
130
. The current I
CP
is dependent on the UP and DN signals from the phase detector
110
. When the rising edge of CLK
ref
leads the rising edge of CLK′
out
, the charge pump circuit
120
increases I
CP
to develop a larger V
c
across the loop filter
130
which, in turn, causes the VCO
140
to increase the frequency of CLK
out
. Conversely, when CLK
ref
lags CLK′
out
, the charge pump
120
decreases I
CP
to develop a smaller V
c
across the loop filter
130
which, in turn, causes the VCO
140
to decrease the frequency of CLK
out
. When the feedback frequency F′
out
is ultimately locked onto the reference frequency F
ref
, i.e. the phases of the two signals CLK
ref
, CLK′
out
are aligned, the voltage V
c
is not adjusted and the output frequency F
out
is kept constant. In this state, the charge-pump PLL
100
is said to be in a “locked” condition.
The charge pump circuit
120
internally delivers a pump-up current and a pump-down current in response to the UP and DN signals. Therefore, the charge pump output current I
CP
is the sum of the pump-up and pump-down currents. Ideally, if the PLL
100
is “locked” and no change in the output frequency F
out
is needed, the pump-up current and the pump-down current would cancel each other and no net current I
CP
would be produced. Nevertheless, manufacturing process variations, ambient conditions and inherent device characteristics can cause the pump-up current and the pump-down current to mismatch. This current mismatch results in a residual charge being left on the loop filter
130
and further causes the voltage V
c
applied to the VCO
140
to fluctuate. As a result, the PLL output signal CLK
out
produces clock jitter. In addition to current mismatch, charge injection and loop filter leakage are sources of charge accumulation on the loop filter
130
which prevent the PLL
100
from being precisely locked.
In view of the above, there is a need for a charge-pump PLL that overcomes the problems of the prior art.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a charge-pump PLL with charge calibration to eliminate a residual charge so that the PLL keeps its output frequency constant.
According to one aspect of the invention, a charge-pump PLL circuit with charge calibration includes a first charge pump circuit and a calibration circuit. The first charge pump provides a first current to cause an output clock signal's phase to track a reference clock signal's phase. The calibration circuit is constructed of a second charge pump circuit and a charge sensing circuit. The second charge pump circuit provides a second current to simulate the first current in a condition in which the phase of the output clock signal is locked onto the phase of the reference clock signal. According to a first and second net charge generated by the first and the second currents separately, the charge sensing circuit generates a calibration voltage signal and provides it as feedback to the first charge pump and the second charge pump. Under control of the calibration voltage signal, the first and the second charge pumps circuit respectively regulate the first net charge and the second net charge to become exactly zero thereby maintaining the phase of the output clock signal locked onto the phase of the reference clock signal.
Preferably, the first charge pump circuit includes a first transistor having its gate coupled to receive the calibration voltage signal for fine tuning the first current based on the calibration voltage signal to eliminate the first net charge. The second charge pump circuit also includes a second transistor having its gate coupled to receive the calibration voltage signal for fine tuning the second current based on the calibrate voltage signal to eliminate the second net charge.
In one embodiment of the present invention, a charge-pump PLL with charge calibration is provided. The charge-pump PLL includes a first charge pump circuit and a calibration circuit. The first charge pump circuit provides a first current to cause an output clock signal's phase to track a reference clock signal's phase. The calibration circuit is constructed of a second phase detector, a second charge pump circuit, and an operational amplifier. The second phase detector receives the reference clock signal and generates a second pump-up pulse and a second pump-down pulse simultaneously at a rate of the reference clock signal. The second charge pump circuit is coupled to the second phase detector. In response to the second pump-up and the second pump-down pulses, the second charge pump circuit provides a second current so as to simulate the first current in a condition in which the phase of the output clock signal is locked onto the phase of the reference clock signal. The operational amplifier has a first input terminal coupled to an output terminal of the first charge pump and has a second input terminal coupled to an output terminal of the second charge pump circuit. In addition, the operational amplifier also has an output terminal connected to a control node of the first charge pump and a control node of the second charge pump respectively. The operational amplifier is used to provide a calibration voltage signal as feedback to the first charge pump circuit and the second charge pump circuit. Under control of the calibration voltage signal, the first and the second charge pumps respectively regulate a first net charge on the first input terminal of the operational amplifier and a second net charge on the second input terminal of the operational amplifier to become exactly zer
Callahan Timothy P.
Luu An T.
Rabin & Berdo P.C.
Via Technologies Inc.
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