Charge-pump phase locked loop circuit

Details Charge-pump phase locked loop circuit Charge-pump phase locked loop circuit

1991-09-20

1993-03-09

Sikes, William L.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307510, H04K 513, G05F 500

Patent

active

051929163

ABSTRACT:
A charge-pump phase locked loop circuit is disclosed that is capable of operating with a high bandwidth while having a low associated noise jitter characteristic. In addition, the phase locked loop circuit has a high dynamic range and prevents against false locking to sub-harmonic frequencies. Furthermore, common mode noise rejection and other internal noise rejection characteristics are optimized.

REFERENCES:
patent: 4222013 (1980-09-01), Bowers et al.
patent: 4484295 (1984-11-01), Bedard et al.
James Miller et al., "High Performance Circuits for the 1486.TM. Processor", 1989 IEEE, pp. 188-192.
Mark G. Johnson et al., "A Variable Delay Line PLL for CPU-Coprocessor Synchronization", IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1218-1223.
Mark G. Johnson et al., "A Variable Delay Line Phase Locked Loop for CPU-Coprocessor Synchronization", 1988 IEEE International Solid-State Circuits Conference, Feb. 1988, pp. 142-143, 334-335.
Deog-Kyoon Jeong, et al., "Design of PLL-Based Clock Generation Circuits", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2, Apr. 1987, pp. 255-261.
Rob Woudsma et al., "The Modular Design of Clock-Generator Circuits in a CMOS Building-Block System", IEEE Journal of Solid-State Circuits, vol. SC-20, No. 3, Jun. 1985, pp. 770-774.
Floyd M. Gardner, "Phase Accuracy of Charge Pump PLL's", IEEE Transactions on Communications, vol. COM-30, No. 10, Oct. 1982; pp. 2362-2363.
Floyd M. Gardner, "Charge-Pump Phase-Lock Loops", IEEE Transactions on Communications, vol. COM-28, No. 11, Nov. 1980, pp. 1849-1858.

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