Charge pump having high switching speed and low switching noise

Details Charge pump having high switching speed and low switching noise Charge pump having high switching speed and low switching noise

1997-05-27

1998-06-16

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

327157, G05F 110

Patent

active

057677360

ABSTRACT:
Briefly, in accordance with one embodiment of the invention, a charge pump comprises: a plurality of transistors coupled in a transistor circuit configuration. The transistor circuit configuration is adapted to be coupled to an electronic circuit. The plurality of transistors are coupled so as to deliver electrical charge to the electronic circuit in response to applied signals as the difference of two substantially predetermined currents.

REFERENCES:
patent: 4677323 (1987-06-01), Marsh
patent: 4847519 (1989-07-01), Wahl et al.
patent: 5196739 (1993-03-01), Sandhu et al.
patent: 5266842 (1993-11-01), Park
patent: 5343088 (1994-08-01), Jeon
patent: 5362990 (1994-11-01), Alvarez et al.
patent: 5453680 (1995-09-01), Giolma et al.
patent: 5459653 (1995-10-01), Seto et al.
patent: 5473283 (1995-12-01), Luich
patent: 5481221 (1996-01-01), Gariboldi et al.
Masayuki Mizuno et al., "A 0.18 .mu.m CMOS Hot-Standby Phase-Locked Loop Using a Noise-Immune Adaptive-Gain Voltage-Controlled Oscillator," ISSCC95/Session 15/Frequency Synthesizers/Paper FA 15.6.
Iiya Novof et al., "Fully-Integrated CMOS Phase-Locked Loop with 15 to 240MHz Locking Range and .+-.50ps Jitter," ISSC95/Session 6/Digital Design Elements/Paper TA 6.5.
John F. Ewen et al., "Single-Chip 1062/Mbaud CMOS Transceiver for Serial Data Communication," ISSCC95/Session 2/Data Communications/Paper WP 2./1.
Trudy Stetzler et al., "A 2.7V to 4.5V Single-Chip GSM Transceiver RF Integrated Circuit," ISSCC95/Session 8/Wireless Communications/Paper TA 8.8.
Alex Waizman, "Delay Line Loop for Frequency Synthesis of De-Skewed Clock," ISSCC95/Session 18/High Performance Logic and Circuit Techniques/Paper 18.5.
A. Terukina et al., "A High Precision(+/-31 100ppm) CMOS Clock Generator for Optimum Sampling of Analog RGB Data," IEEE 1993 Custom Integrated Circuits Conference, pp. 27.3.1-27.3.5.
M. J. Bayer et al., "Cell Based Fully Integrated CMOS Frequency Synthesizers," IEEE 1993 Custom Integrated Circuits Conference, pp. 27.2.1-27.2.3.
Avner Efendovich et al., "Multi-Frequency Zero-Jitter Delay-Locked Loop," IEEE 1993 Custom Integrated Circuits Conference, pp. 27.1.1-27.1.4.
Michael Franz et al., "A 240MHz Phase-Locked-Loop Circuit Implemented as a Standard Macro on CMOS SOG Gate Arrays," IEEE 1992 Custom Integrated Circuits Conference, pp. 25.1.1-25.1.4.
Ricky F. Bitting et al., "A 30-128MHz Frequency Synthesizer Standard Cell," IEEE 1992 Custom Integrated Circuits Conference, pp. 24.1.1-24.1.6.
Edward Liu et al., "Behavorial Representations for VCO and Detectors in Phase-Lock Systems," IEEE 1992 Custom Integrated Circuits conference, pp. 12.3.1-12.3.4.
Ian A. Young et al., "A PLL CLock Generator with 5 to 110MHz of Lock Range for Microprocessors," IEEE Journal of Solid State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1599-1607.
Beomsup Kim et al., "A 30-MHz Hybrid Analog/Digital Clock Recovery Circuit in 2 .mu.m CMOS," IEEE Journal of Solid State Circuits, vol. 25, No. 6, Dec. 1990, pp. 1385-1394.
Mehmet Soyuer et al., "Frequency Limitations of a Conventional Phase-Frequency Detector," IEEE Journal of Solid State Circuits, vol. 25, No. 4, Aug. 1990, pp. 1019-1022.
Kurt M. Ware et al., "A 200-MHz CMOS Phase-Locked Loop with Dual Phase Detectors," IEEE Journal Of Solid State Circuits, vol. 24, No. 6 Dec. 1989, pp. 1560-1568.
Sam Yinshang et al., "An Analog PLL-Based Clock and Data Recovery Circuit with High Input Jitter Tolerance," IEEE Journal of Solid State Circuits, vol. 24, No. 2, Apr. 1989, pp. 325-330.
Mark G. Johnston et al., "A Variable Delay Line PLL for CPU-Coprocessor Synchronization," IEEE Journal of Solid--State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1218-1223.
Deog-Kyoon Jeong et al., "Design of PLL-Based Clock Generation Circuits," IEEE Journal of Solid State Circuits, vol. SC-22, No. 2, Apr. 1987, pp. 255-261.
Milton E. Wilcox, "A 2-V Amplitude-Linear Phase-Locked Loop," IEEE Journal of Solid State Circuits, vol. SC-21, No. 6, Dec. 1986, pp. 934-939.

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