Charge pump for word lines in programmable semiconductor memory

Static information storage and retrieval – Floating gate – Particular biasing

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36518523, 36518909, G11C 1604

Patent

active

06069825&

ABSTRACT:
A self-decoding charge pump for charging word lines or bit lines of a semiconductor memory array such as an EEPROM includes a passive, parallel-plate ONO capacitor for coupling voltage pulses generated by an oscillator to a charge transfer node. The voltage pulses received at the charge transfer node control the transfer of increments of charge from a high-voltage generator to a selected word line. Large-area capacitive coupling may be used without causing significant carrier injection into the substrate. In one configuration exploiting the floating-gate EEPROM semiconductor geometry, plural stacked capacitors are used, allowing a doubling of the capacitance per surface area relative to a single-capacitor configuration. Plural oscillators generating lower-amplitude signals can be used with one high-voltage generator.

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patent: 4511811 (1985-04-01), Gupta
patent: 4673829 (1987-06-01), Gupta
patent: 4701637 (1987-10-01), Piro
patent: 4811292 (1989-03-01), Watanabe
patent: 4823317 (1989-04-01), Brahmbhatt
patent: 4831589 (1989-05-01), Brahmbhatt
patent: 5394365 (1995-02-01), Tsukikawa

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