Charge pump for PLL/DLL

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

C327S148000, C375S374000

Reexamination Certificate

active

07408391

ABSTRACT:
A charge pump for use in a Phase Locked Loop/Delay Locked Loop. The charge pump includes a pull-up circuit a pull-down circuit and a reference current source. The reference current source includes a number of select transistors and a number of mirror master transistors. The mirror master transistors are coupled to slave transistors in either of the pull-up circuit and the pull-down circuit.

REFERENCES:
patent: 5233314 (1993-08-01), McDermott et al.
patent: 5362990 (1994-11-01), Alvarez et al.
patent: 5473283 (1995-12-01), Luich
patent: 5933037 (1999-08-01), Momtaz
patent: 6124755 (2000-09-01), Parker et al.
patent: 6160432 (2000-12-01), Rhee et al.
patent: 6229362 (2001-05-01), Choi
patent: 6278332 (2001-08-01), Nelson et al.
patent: 6316987 (2001-11-01), Dally et al.
patent: 6512404 (2003-01-01), Ruegg et al.
patent: 6535051 (2003-03-01), Kim
patent: 6603340 (2003-08-01), Tachimori
patent: 6617936 (2003-09-01), Dally et al.
patent: 6636098 (2003-10-01), Kizer
patent: 6664829 (2003-12-01), Hughes
patent: 6667641 (2003-12-01), Wang et al.
patent: 6710665 (2004-03-01), Maneatis
patent: 6741110 (2004-05-01), Roisen
patent: 6744292 (2004-06-01), Chen et al.
patent: 6771114 (2004-08-01), Watarai
patent: 6861916 (2005-03-01), Dally et al.
patent: 6924992 (2005-08-01), Gaudin et al.
patent: 6954511 (2005-10-01), Tachimori
patent: 7092689 (2006-08-01), Boecker et al.
patent: 2002/0041196 (2002-04-01), Demone et al.
patent: 2003/0076142 (2003-04-01), Ko
patent: 2004/0057546 (2004-03-01), Badets et al.
patent: 0 484 059 (1992-05-01), None
patent: 0 755 120 (1997-01-01), None
patent: 1 292 033 (2003-03-01), None
Duque-Carrillo, J.F., et al, “1-V Rail-to-Rail Operational Amplifiers in Standard CMOS Technology,”IEEE Journal of Solid-State Circuits, vol. 35(1): (Jan. 2000).
Maneatis, J.G., “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,”IEEE Journal of Solid-State Circuits, vol. 31(11) (Nov. 1996).
Kim, C.H., et al., “A 64-Mbit, 640-Mbyte/s Bidirectional Data Strobed, Double-Data-Rate SDRAM with a 40-mW DLL for a 256-Mbyte Memory System,”IEEE Journal of Solid-State Circuits, vol. 33(11): (Nov. 1998).
Moon, Y., et al., “An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance,”IEEE Journal of Solid-State Circuits, vol. 35(3): (Mar. 2000).
Larsson, P., “A 2-1600MHz 1.2-2.5V CMOS Clock-Recovery PLL with Feedback Phase-Selection and Averaging Phase-Interpolation for Jitter Reduction,”IEEE Journal of Solid-State Circuits Conference, (1999).
Lee, J-S., et al., “Charge Pump with Perfect Current Matching Characteristics in Phase-locked Loops,”Electronic Letters, IEE Stevenage, GB, 36(23):1907-1908 (Nov. 2002).

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