Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2003-02-24
2004-11-16
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C363S059000
Reexamination Certificate
active
06819162
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a charge pump for negative voltages.
2. Description of the Related Art
As is known, in many fields of microelectronics, the need to reduce consumption and overall dimensions leads to the use of ever lower supply voltages.
In various cases, however, the dynamics that can be obtained from supply voltages is insufficient to guarantee proper operation of all the parts that make up a given circuit or device. For example, many devices comprising nonvolatile memories, such as memories of EEPROM or flash types, are supplied with voltages of between 0 V and 1.8 V; on the other hand, the circuits for reading and writing said memories normally require higher voltages, of approximately 5-15 V, and hence could not operate with such limited dynamics. In other cases, negative voltages are required, or in any case voltages lower than the minimum supply voltage.
The problem is normally solved by using charge-pump circuits, positive and/or negative ones, which are able to supply voltages having values higher or lower than the maximum dynamics allowed by the supply voltages.
An example of charge pump is described in the U.S. Pat. No. 5,874,850, granted on Feb. 23, 1999 to STMicroelectronics S.r.I., which is incorporated by reference in its entirety.
The contents of said patent will be illustrated briefly hereinafter, with reference to
FIGS. 1 and 2
, in which a charge-pump voltage-boosting circuit is designated as a whole by
1
. The voltage-boosting circuit
1
comprises a voltage-boosting stage
2
, having a low-voltage input terminal
2
a
, a high-voltage output terminal
2
b
, and a first driving terminal
2
c
and a second driving terminal
2
d
; and an oscillator
3
, connected to a supply line
5
and having outputs connected to the first driving terminal
2
c
and the second driving terminal
2
d
, respectively, and supplying a first timing signal CK
1
and a second timing signal CK
2
, respectively, which are in phase opposition with respect to one another.
The voltage-boosting stage
2
has a first branch
6
and a second branch
7
, each of which comprises an NMOS transistor
9
and a PMOS transistor
10
, and a first capacitor
11
and a second capacitor
12
. In each of the two branches
6
,
7
, the NMOS transistors
9
and the PMOS transistors
10
have their source terminals
9
a
and
10
a
, connected to a respective node
13
,
14
and their drain terminals
9
b
,
10
b
, connected, respectively, to the input terminal
2
a
and to the output terminal
2
b
of the voltage-boosting stage
2
. Furthermore, the NMOS transistors
9
and PMOS
10
of the first branch
6
have gate terminals connected to the node
14
of the second branch
7
and, vice versa, the NMOS transistors
9
and PMOS transistors
10
of the second branch
7
have their gate terminals connected to the node
13
of the first branch
6
. The NMOS transistors
9
have well terminals
9
c
connected directly to the respective drain terminals
9
b
and, via incorporated diodes
15
(well diodes or bulk diodes), to the respective source terminals
9
a
. In a dual way, the PMOS transistors
10
have well terminals
10
c
connected directly to the respective source terminals
10
a
and, via incorporated diodes
16
, to the respective drain terminals
10
b
. In each of the branches
6
,
7
, in practice, the incorporated diodes
15
,
16
are connected in series and, when they are biased directly, form conductive paths that facilitate passage of current between the input terminal
2
a
and the output terminal
2
b
of the voltage-boosting stage
2
.
The first capacitor
11
is connected between the first driving terminal
2
c
and the node
13
of the first branch
6
, and the second capacitor
12
is connected between the second driving terminal
2
d
and the node
14
of the second branch
7
.
The charge pump
1
is efficient and has small overall dimensions, but is not suitable for being used as a negative charge pump, since in this case it would present biasing problems.
For greater clarity, reference is made to
FIG. 2
, in which one of the PMOS transistors
10
is shown. The PMOS transistors
10
are made in a substrate
18
, here of type P, and each comprise a well
20
, of type N, in which conductive source regions
21
and conductive drain regions
22
are embedded, both of type P. By means of the drain terminal
10
b
and the well terminal
10
c
, the conductive drain region
22
and the well
20
are connected together directly and hence are always at the same voltage. In
FIG. 2
, the incorporated diodes
16
are shown with dashed line.
In particular, in known charge pumps the biasing of the junction between the internal wells
20
of the PMOS transistors
10
and the substrate
18
is problematical. This junction, in fact, must always remain reverse-biased during operation of the device to prevent one of the parasitic currents being injected from the substrate
18
into the internal wells
20
. For this reason, it is obviously necessary for all the internal wells
20
(of type N) to be set at a voltage higher than the voltage of the substrate
18
(of type P). In particular, given that the substrate
18
must be connected to ground, the internal wells
20
of the PMOS transistors
10
must always be at a positive voltage. On the other hand, in a multi-stage negative charge pump, the input terminals
2
a
and output terminals
2
b
of the stages downstream of the first would be at a negative voltage. The output terminal
2
b
is, however, directly connected to the drain terminals
10
b
of the PMOS transistors
10
and hence also to the wells
20
, which would thus be biased at a negative voltage, lower than the voltage of the substrate
18
. Consequently, the junctions between the substrate
18
and the internal wells
20
of the PMOS transistors
10
would be biased directly, so causing malfunctioning.
BRIEF SUMMARY OF THE INVENTION
An embodiment of the present invention provides a negative charge pump that is free from the drawbacks described above.
The charge pump includes a voltage-boosting stage having symmetrical first and second branches connected between a high-voltage terminal and a low-voltage terminal. Each of the branches includes a respective first transistor and a respective second transistor; wherein said first and second transistors are all triple-well MOS transistors of one and the same polarity type
REFERENCES:
patent: 6107864 (2000-08-01), Fukushima et al.
patent: 6278315 (2001-08-01), Kim
patent: 6359501 (2002-03-01), Lin et al.
patent: 6429723 (2002-08-01), Hastings
patent: 6476666 (2002-11-01), Palusa et al.
patent: 6498527 (2002-12-01), Matsumoto
patent: 2003/0071301 (2003-04-01), Wald et al.
Iannucci Robert
Jorgenson Lisa K.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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