Static information storage and retrieval – Powering
Reexamination Certificate
2001-12-21
2003-07-15
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Powering
C365S159000
Reexamination Certificate
active
06594193
ABSTRACT:
The present application is also related to the following applications, all of which are filed simultaneously herewith, and which are hereby incorporated by reference as if fully set forth herein:
An application entitled “INSULATED-GATE FIELD EFFECT TRANSISTOR INTEGRATED WITH NEGATIVE DIFFERENTIAL RESISTANCE (NDR) FET;” U.S. Ser. No. 10/028,084; and
An application entitled “MEMORY CELL UTILIZING NEGATIVE DIFFERENTIAL RESISTANCE FIELD-EFFECT TRANSISTORS”; U.S. Ser. No. 10/029,077; and
An application entitled “DUAL MODE FET & LOGIC CIRCUIT HAVING NEGATIVE DIFFERENTIAL RESISTANCE MODE”; U.S. Ser. No. 10/028,394.
An application entitled “IMPROVED NEGATIVE DIFFERENTIAL RESISTANCE FIELD EFFECT TRANSISTOR (NDR-FET) & CIRCUITS USING THE SAME”; U.S. Ser. No. 10/028,085.
FIELD OF THE INVENTION
This invention relates to semiconductor devices and more particularly to a charge pump that is useable with a negative differential resistance (NDR) FET. The present invention is applicable to a wide range of semiconductor integrated circuits, particularly for applications where it is desirable to achieve a high level of functional integration using NDR devices without the need for multiple operating voltages.
BACKGROUND OF THE INVENTION
A new type of CMOS compatible, NDR capable FET is [described in the aforementioned applications to King et al. referenced above] disclosed in the following King et al. applications: Ser. No. 09/603,101, now U.S. Pat. No. 6,512,274 issued on Jan. 28, 2003, entitled “A CMOS-PROCESS COMPATIBLE, TUNABLE NDR (NEGATIVE DIFFERENTIAL RESISTANCE) DEVICE AND METHOD OF OPERATING SAME”; and Ser. No. 09/603,102, now U.S. Pat. No. 6,479,862 isued on Nov. 12, 2002, entitled “CHARGE TRAPPING DEVICE AND METHOD FOR IMPLEMENTING A TRANSISTOR HAVING A NEGATIVE DIFFERENTIAL RESISTANCE MODE”: and Ser. No. 09/602,658 entitled “CMOS COMPATIBLE PROCESS FOR MAKING A TUNABLE NEGATIVE DIFFERENTIAL RESISTANCE (NDR) DEVICE all of which were filed Jun. 22, 2000 and which are hereby incorporated by reference as if fully set forth herein. The advantages of such device are well set out in such materials, and are not repeated here. In preferred embodiments, this device typically uses a gate bias voltage that is higher than that used by an equivalent logic gate or memory gate that might be incorporated with such NDR device. In some environments, it may not be possible and/or desirable to incorporate an additional external voltage supply having a bias voltage sufficient to operate an NDR FET of the type described in King et al.
As supply voltages have dropped in other semiconductor devices, designers have turned on many occasions to charge pumps to facilitate generating a sufficiently high operating voltage. They are used, for example, in numerous EEPROM devices for programming and erase operations. Nonetheless, to date no one has proposed using such structures with an NDR capable FET.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide an efficient and scaleable charge pump that can be used (and integrated) with an NDR FET, including those types described in King et al.
These and other objects are achieved by the present invention that includes an integrated circuit (IC) device comprising a semiconductor field effect transistor (FET) adapted to exhibit a negative differential resistance (NDR) effect in response to a bias signal applied to a gate terminal. The semiconductor FET is preferably a three terminal device including the gate terminal, a source terminal, and a drain terminal. The NDR effect is exhibited in a channel coupling the source/drain regions of the FET. A conventional charge pump circuit can be used for supplying the bias signal. In this manner, a simple bias signal having a voltage value greater than an operating voltage used by other logic devices and/or memory devices is incorporated in the IC device, and yet allows for an NDR capability in such IC.
In a preferred embodiment, the charge pump circuit, semiconductor FET, and logic devices and/or memory devices are formed during a common set of MOS compatible semiconductor fabrication processes. In another variation, the charge pump further supplies an operating voltage for a nonvolatile memory array, such as a flash array that may be embedded in a System on chip (SOC) implementation. Because the inventive NDR FET consumes little power, the charge pump uses a reduced amount of current for supplying the bias voltage than that required for providing a similar bias voltage to an equivalent number of flash memory cells for a program, erase or read operation.
The charge pump can include any number of desired stages, with each stage including at least one transistor and one capacitor generating an intermediate output voltage that is passed to a subsequent stage. In some applications, each stage uses a clock signal that differs from any clock signal used by any other stage. Furthermore, it is possible to selectively enable the charge pump, to save power, depending on whether an NDR capability is operational in the IC device.
In a similar fashion, an improved method of operating an NDR FET with a bias voltage generated by a charge pump is also disclosed.
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Gross J. Nicholas
Lebentritt Michael S.
Phung Anh
Progressent Technologies, Inc.
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