Charge pump for low-voltage, low-jitter phase locked loops

Details Charge pump for low-voltage, low-jitter phase locked loops Charge pump for low-voltage, low-jitter phase locked loops

2000-02-15

2001-08-21

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S008000, C331S025000, C327S156000, C327S157000, C327S108000, C327S111000

Reexamination Certificate

active

06278332

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to charge pumps used in phase-locked loops (PLLs) and, in particular, to low-voltage charge pumps for use in low-voltage, low-jitter PLLs.
2. Description of the Related Art
Phase-locked loop (“PLL”) circuits are widely used in a variety of applications. A PLL typically produces an output signal of substantially the same frequency as a reference signal, with a predetermined phase relation to the reference signal. A PLL can be used wherever it is necessary to synchronize the phase and/or frequency of two signals. For example, a PLL may be used to provide a frequency synthesizer which generates an output signal whose frequency bears a specified relationship to the frequency of an input reference signal. This may be used to generate an output clock signal having an accurate frequency, for example, based on an input clock signal having a known frequency. PLL circuits are often used in other types of signal processing circuits as well, such as AM and FM radios, televisions, wireless communication equipment, and multiplex stereo demodulating circuits. In a typical communications application, for example, a PLL is used to synchronize a local oscillator to the frequency (and/or phase) of an incoming data signal.
In one application, a PLL may be used to tune a high frequency local oscillator to a separate, more stable, lower-frequency local oscillator. For example, a very high frequency signal may be necessary for synchronizing to an incoming radio frequency signal at, for example, 800 MHz. Crystal oscillators are very stable and accurate, but typically do not operate at high enough frequencies to be used directly for high radio frequency applications. Thus, a high frequency voltage-controlled oscillator (VCO) may be utilized, which generates the desired high frequency very precisely, by placing the VCO in a PLL with a crystal oscillator.
A PLL typically comprises a phase and/or frequency comparator (e.g., a phase detector [PD] or sequential-logic, phase/frequency detector [PFD]), which receives and compares an external input or “reference” signal (or a divided version of this signal) to the output “feedback” signal generated by a VCO (or a divided version of this signal). The PD or PFD generates logic “up” (fast, or phase-leading) and “down” (slow, or phase-lagging) signals, to either speed up or slow down the feedback signal. The PLL also typically comprises a “charge pump” for receiving the up and down signals output by the PD or PFD, and a low pass “loop” filter coupled to the output of the charge pump, to provides an analog output control voltage to the VCO. A common form of VCO for use in a PLL is a ring oscillator that employs a series of delay elements to provide the desired frequency range of operation. Thus, a charge pump usually accompanies a PFD, and, along with a loop filter incorporated into or attached to the output of the charge pump, converts the PFD's output logic states into analog signals suitable for controlling the VCO.
Referring now to
FIG. 1
, there is shown a block diagram illustrating a conventional PLL frequency synthesizer circuit
100
. As shown, PLL circuit
100
comprises an initial ÷N unit
101
, which receives input clock signal I
CLK
, having an input frequency. Divider unit
101
divides the input clock signal I
CLK
to provide internal or common denominator reference clock signal RF
CLK
, which has 1/N the frequency of the input clock signal. Phase frequency detector (PFD)
102
receives this reference clock signal RF
CLK
as well as the feedback clock signal FB
CLK
, which has been produced by dividing the output of VCO
105
by M with divider unit
107
. Thus, the output of VCO
105
is nominally M times the frequency of RF
CLK
, or M/N times the frequency of I
CLK
. The output of VCO
105
is divided by P by divider unit
106
, to provide an output clock signal O
CLK
having a frequency which is M/(N·P) times the frequency of I
CLK
.
Typically, the output clock signal and the input clock signal are each multiples of some common, lower frequency. For example, if the input clock I
CLK
is 10 MHz, and the desired output clock O
CLK
is 25 MHz, they are both multiples of 5 MHz. Thus, the common-denominator frequency 5 MHz may be used as the comparison frequency for PFD
102
. To achieve this, N=2, and, for a VCO producing a nominally 50 MHz output signal, P=2 and M=10, in an embodiment.
Thus, in the PLL, the 10 MHz input clock signal may be divided by 2 to provide a “common denominator” reference signal 5 MHz signal, and the 25 MHz output clock signal may be divided by 5 to provide a feedback signal of nominal frequency 5 MHz, for comparison by the PFD. (Alternatively, the VCO may itself generate a higher frequency, such as 50 MHz, which is divided by 2 to provide the 25 MHz output clock signal, and divided by 10 to provide the 5 MHz feedback signal.) PLLs and lock detection techniques are described in further detail in Floyd Martin Gardner,
Phaselock Techniques,
2nd ed. (Wiley 1979); Roland E. Best,
Phase
-
Locked Loops
(McGraw-Hill 1993); C. R. Hogge, “A Self Correcting Clock Recovery Circuit,”
Journal of Lightwave Technology,
Vol. LT-3, No. 6 (December 1985), pp. 1312-1314.
PFD
102
forms a difference signal by comparing the signal based on the external input signal (i.e. RF
CLK
) and the signal based on the VCO signal (i.e. FB
CLK
). In one type of PFD, the difference signal consists of UP (fast) and DOWN (slow) pulse signals, which are applied to the charge pump
103
. The charge pump generates charge based on the UP or DOWN signals, which charge is integrated by the loop filter
104
to produce a DC control voltage V
CONT
. This DC control voltage controls the output frequency of the VCO. I.e., the charge pump combined with the loop filter converts the timed output logic levels from digital type PDs or PFDs into analog quantities for controlling the VCO.
When the frequency and phase of the signals compared by the PFD are substantially identical, the PLL is said to be in a state of lock (both frequency and phase lock). Because of the closed loop nature of a PLL and the negative feedback employed, the output frequency of the VCO is maintained to closely match the frequency of the reference input signal. A PLL may be used, therefore, to cause the output signal of the VCO to be locked to a stable reference frequency. For this reason, a PLL is often employed to generate an output reference signal, at a desired frequency, that is frequency and phase locked relative to some input reference signal. Charge pumps are further discussed in F. M. Gardner, “Charge-Pump Phase-Lock Loops,”
IEEE Trans. Comm.,
vol. COM-28, pp. 1849-1858 (November 1980); and Behzad Razavi, ed.,
Monolithic Phase
-
Locked Loops and Clock Recovery Circuits:
Theory and Design (IEEE Press, 1996): pp. 1-39.
Referring now to
FIG. 2
, there is shown a block diagram illustrating charge pump sharing in a charge pump and loop filter
200
. The digital signals UP, DN from a PFD such as PFD
102
of
FIG. 1
switch current sources I
UP
and I
DN
onto the output node, thus delivering a charge to move the output control voltage V
CONT
up or down. Once the loop is locked, the charge pump
103
will only need to deliver extremely narrow output current pulses to the loop filter
104
to correct for voltage drop in the loop filter due to leakage. Even after lock is achieved, however, a charge sharing effect occurs when switches S
1
and S
2
are switched off and on. During the time when S
1
and S
2
are off, I
UP
and I
DN
pull nodes X and Y to V
DD
and ground, respectively; this causes charge-sharing between parasitic capacitors Cx and Cp, and Cy and Cp, when S
1
and S
2
turn on again, respectively. If V
CONT
=V
DD
/2, I
UP
=I
DN
, and Cx=Cy, then V
CONT
is not disturbed (not changed). However, because V
CONT
determines the VCO frequency, it is generally not equal to V
DD
/2, thus experiencing a jump when S
1
and S
2
tu

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