Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-03-12
2001-01-16
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S534000
Reexamination Certificate
active
06175264
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a charge pump and, more particularly to a charge pump incorporated in a semiconductor non-volatile memory device such as, for example, an electrically erasable and programmable read only memory device and a semiconductor structure for the charge pump circuit.
DESCRIPTION OF THE RELATED ART
A flash-erase memory device is a kind of the electrically erasable and programmable read only memory device, and is abbreviated as “flash EEPROM” hereinbelow.
FIG. 1
illustrates the structure of a standard nonvolatile memory cell incorporated in the flash EEPROM device. N-type source/drain regions
1
/
2
are formed in a p-type silicon substrate
3
, and a tunnel gate oxide layer
4
, a floating gate electrode
5
, an interpoly oxide layer
6
and a control gate electrode
7
are laminated on a channel region between the n-type source region
1
and the n-type drain region
2
.
The floating gate electrode
5
is electrically isolated from another conductive layer, and electron is accumulated in and evacuated from the floating gate electrode
5
. If the electron is accumulated in the floating gate electrode
5
, the accumulated electron induces holes in the channel region, and the memory cell has a high threshold with respect to the potential level on the control gate electrode
7
. On the other hand, when the electron is evacuated from the floating gate electrode
5
, the memory cell is recovered to a low threshold. When the memory cell is changed to the erased state, the n-type source region
1
and the control gate electrode
7
are, by way of example, biased to +5 volts and −10 volts, respectively, and the n-type drain region
2
is maintained in floating state. The two kinds of threshold are corresponding to the logic levels of a data bit. Thus, the data bit is stored in the form of the threshold of the memory cell.
FIG. 2
illustrates another kind of the non-volatile memory cell. A p-type well
11
is nested in an n-type well
12
, which is formed in a surface portion of a p-type semiconductor substrate
13
. A heavily-doped p-type region
14
and an heavily-doped n-type region
15
are respectively formed in the p-type well
11
and the n-type well
12
, and both of the heavily-doped p-type region
14
and the heavily-doped n-type region
15
are electrically connected to each other.
An n-type source region
16
and an n-type drain region
17
are formed in the p-type well
11
, and are spaced from each other. A tunnel gate oxide layer
18
, a floating gate electrode
19
, a interpoly oxide layer
20
and a control gate electrode
21
are stacked over the channel region between the n-type source region
16
and the n-type drain region
17
.
The prior art non-volatile memory cell also changes the threshold depending upon the amount of electron accumulated in the floating gate electrode
19
. When the electron is evacuated from the floating gate electrode, a negative potential Vg and a positive potential Vb are respectively applied to the control gate electrode
21
and the p-type well
11
, and the accumulated electron flows through the tunnel gate oxide layer
18
to the p-type well
11
. In this instance, the negative potential Vg is −10 volts, and the positive potential Vb is +5 volts.
Thus, the prior art non-volatile memory cells requires various bias voltages for rewriting the data bit stored therein. The ground voltage GND and the positive power voltage Vcc of 3 or 5 volts are supplied to the flash EEPROM device. However, the other bias voltage such as Vg=−10 volts is internally generated. The prior art flash EEPROM device is equipped with a charge pump circuit, and the charge pump circuit generates the negative voltage Vg.
A typical example of the charge pump circuit is disclosed in Japanese Patent Publication of Unexamined Application NO. 8-103070 and “A 5-V-Only Operation 0.6-&mgr;m Flash EEPROM with Row Decoder Scheme in Triple-Well Structure”, IEEE Journal of Solid-State Circuit, vol. 27, No. 11, November 1992, pages 1540-1546. Those prior art charge pump circuits will be described hereinlater.
FIG. 3
illustrates the prior art charge pump circuit disclosed in the Japanese Patent Publication of Unexamined Application. P-channel enhancement type field effect transistors MP
0
/MP
1
/MP
2
/MP
3
/MP
4
are connected in series between a ground line GND and an output node Vncp. The p-channel enhancement type field effect transistor MP
0
has a gate electrode connected to the drain node thereof, and capacitors C
1
/C
2
/C
3
/C
4
are associated to the p-channel enhancement type field effect transistors MP
1
/MP
2
/MP
3
/MP
4
. Each of the capacitor C
1
/C
2
/C
3
/C
4
is connected to the gate electrode and the drain node of the associated p-channel enhancement type field effect transistor MP
1
/MP
2
/MP
3
/MP
4
. A clock signal FA is 180 degrees different in phase from another clock signal FB, and the clock signals FA and FB are supplied to the capacitors C
1
/C
3
and the capacitors C
2
/C
4
, respectively.
The p-channel enhancement type field effect transistors MP
0
/MP
1
/MP
2
are fabricated on an n-type well, and the other p-channel enhancement type field effect transistors MP
3
/MP
4
are fabricated on another n-type well. A positive power voltage Vcc is supplied to the n-type well assigned to the p-channel enhancement type field effect transistors MP
0
/MP
1
/MP
2
, and the ground line is connected to the n-type well assigned to the other p-channel enhancement type field effect transistors MP
3
/MP
4
. The reason why the ground voltage is supplied to the n-type well assigned to the p-channel enhancement type field effect transistors MP
3
/MP
4
is that the ground voltage restricts the increase of the threshold due to the back-gate biasing effect in the p-channel enhancement type field effect transistors MP
3
/MP
4
. As a result, the p-channel enhancement type field effect transistors MP
3
/MP
4
do not widely reduce the boosting efficiency. Thus, the prior art charge pump circuit achieves a fairly good boosting efficiency by virtue of the ground voltage applied to the n-type well assigned to the p-channel enhancement type field effect transistors MP
3
/MP
4
.
In operation, the clock signals FA/FB are alternated between the positive power voltage Vcc and the ground level GND as shown in FIG.
4
. When the clock signal FA is changed from the ground level GND to the positive power voltage Vcc and, thereafter, vice versa, the other clock signal FB is changed from the positive power voltage Vcc to the ground level and vice versa. Thus, the clock signal FA is 180 degrees different in phase from the other clock signal FB. The capacitors C
1
/C
2
/C
3
/C
4
cooperate with the parasitic capacitors of the p-channel enhancement type field effect transistors MP
1
/MP
2
/MP
3
/MP
4
, respectively, and the capacitors C
1
-C
4
and the associated p-channel enhancement type Field effect transistors MP
1
-MP
4
form four boosting stages. The clock signals FA/FB cause the four stages to stepwise boost the potential level at the drain nodes, and the boosting stages produce a negative voltage at the output node Vncp.
FIG. 5
illustrates the prior art charge pump circuit disclosed in the IEEE Journal of Solid-State. P-channel enhancement type field effect transistors MP
1
/MP
2
/MP
3
/MP
4
/MP
5
are connected in series between a ground line GND and an output node Vncp, and other p-channel enhancement type field effect transistors MP
11
/MP
12
/MP
13
/MP
14
are connected between the gate electrodes of the p-channel enhancement type field effect transistors MP
1
/MP
2
/MP
3
/MP
4
and the associated drain nodes thereof. Capacitors C
1
/C
2
/C
3
/C
4
are connected to the gate electrodes of the p-channel enhancement type field effect transistors MP
11
/MP
12
/MP
13
/MP
14
and to the drain nodes of the p-channel enhancement type field effect transistors MP
2
/MP
3
/MP
4
/MP
5
. Other capacitors C
11
/C
12
/C
13
/C
14
are connected to the gate electrodes of the p-channel enhancement type field effect transistors
Cunningham Terry D.
NEC Corporation
Tra Quan
Young & Thompson
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