Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2002-05-09
2004-01-13
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
Reexamination Certificate
active
06677806
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a charge pump for generating high voltages for integrated semiconductor circuits, having a plurality of pump stages each having at least one power transistor for generating a pump voltage on a power path. The power transistor has a freely connectable bulk terminal, with which a well structure of the power transistor can be held at a predetermined potential via a well charging path that is substantially separate from the power path. In order to generate the predetermined potential, a first and a second well charging transistor are switched into the well charging path. The well charging transistors are connected in series, their junction point being connected to the bulk terminal of the power transistor and the outer terminals of the series circuit being connected in parallel with the outputs of the power transistor. A pump capacitor is connected between two pump stages in each case.
In the context of this description, the term “high voltages” refers to voltages whose magnitude is greater than a positive and/or negative supply voltage Vdd/Vss that is present at the relevant integrated semiconductor circuit. Such high positive and also negative voltages are required in most modern semiconductor circuits. This relates, in particular, to those circuits which comprise memories such as, for example, EEPROMs, DRAMs, FRAMs, etc. Furthermore, specific applications such as e.g. contactless systems such as mobile phones, chip cards, smartcards or wire-free devices appertaining to medical technology lead to ever smaller designs (0.25 &mgr;m, 0.18 &mgr;m) in the semiconductor technology of the integrated circuits, so that it is necessary also to reduce the supply voltages further and further (2.5 volts, 1.8 volts, 1 volt) and, consequently, charge pumps are required which must be evermore powerful in order to generate the high voltages mentioned in the introduction. Since the applications are generally battery-operated, it is desirable, moreover, for the total energy consumption to be kept as low as possible in order to enable a long operating duration.
In a semiconductor process, the basic elements are constructed from p- and n-doped regions with different doping, thereby producing a number of pn junctions and pnp and npn transistors. In a standard application, generally only positive voltages with a maximum level of Vdd and negative voltages with a minimum level of Vss are used with the basic elements (PMOS, NMOS, R, C), the standard situation being that the n-type well of the PMOS transistors is connected to Vdd and the p-type well of the NMOS transistors is connected to Vss. Consequently, in accordance with the specification, the pn junctions are expediently always reverse-biased and the pnp and npn transistors are always in the off state. However, as soon as voltages which differ from the voltages Vdd and Vss are required, special circuit concepts are necessary in order, with the basic elements then no longer connected up in a specification-forming manner, to keep the pn junctions and the pnp and npn transistors turned off. Thus, in an n-type well process, for example, the n-type well, which contains at least one p-doped channel of a PMOS transistor, is not permitted to be charged negatively since the n-type well/p-type substrate junction constitutes a forward-biased pn diode. Correspondingly, the well potential is not permitted to become lower than the voltage potential at a contact set into the well (positive base-emitter voltage, pnp transistor, p+-type contact
-type well/p-type substrate).
Firstly, two prior art charge pumps which have been used previously in attempts to avoid these problems will be explained with reference to
FIGS. 5
to
8
.
FIG. 5
shows the circuit of a charge pump for negative output voltages, while
FIG. 7
illustrates a corresponding circuit for positive output voltages.
FIGS. 6 and 8
in each case show a timing scheme for the driving of the circuit in accordance with FIG.
5
and
FIG. 7
, respectively.
The circuits are each composed of N+1 pump stages x which are connected in a series and together form a power path. A supply voltage Vdd is present at the input of the circuit, from which supply voltage the pump voltage Vpmp is generated, which charges a charging capacitor Cload at the output of the charge pump. In this case, the switching elements of a pump stage x are respectively designated by the same second index x.
The charge transport to the load capacitor Cload is effected via a plurality of power transistors M
1
x and pump capacitors Cpx in each pump stage x, which are alternately turned on and turned off and alternately charge and discharge the pump capacitors. For the driving of a power transistor M
1
x, each pump stage x furthermore has a control transistor M
2
x and a boost capacitor Cbx, which form a control circuit. An external clock generator (not illustrated) feds to those terminals of the pump and boost capacitors which are designated by F
1
to F
4
in
FIGS. 5 and 7
. The clock signals, in each case designated identically, in accordance with
FIGS. 6 and 8
, respectively. These illustrations are intended only to make it clear at what instance signals with a high or low level are present at the individual capacitors Cbx, Cpx of two successive pump stages.
In detail, during a first clock phase t
1
, a clock signal with a low level is present at the pump capacitor Cp
2
of the second stage and the boost capacitor Cb
1
of the first stage, and a clock signal with a high level is present at the pump capacitor Cp
1
of the first stage and the boost capacitor Cb
2
of the second stage.
In this case, the power transistor M
11
of the first stage carries the required charge, while the control transistor M
21
of the first stage serves for precharging the gate of the power transistor during the first clock phase t
1
.
During a second clock phase t
2
, wherein a clock signal with a low level is fed to the pump capacitor Cp
1
of the first stage and to the boost capacitor Cb
2
of the second stage and a clock signal with a high level is present at the pump capacitor Cp
2
of the second stage and the boost capacitor Cb
1
of the first stage, the control transistor M
21
of the first stage is closed, and the potential at the gate of the power transistor M
11
is reduced by at most the supply voltage Vdd by means of a boost pulse at the boost capacitor Cb
1
. As a result, the power transistor M
11
opens particularly well, and the voltage drop across this transistor M
11
can be minimized.
However, a first problem here is that this mechanism operates reliably only for as long as, in the first clock phase, the gate-source voltage (Vgs voltage) of the control transistor M
21
(which corresponds to the drain-source voltage across the power transistor M
11
) is greater than the threshold voltage of the PMOS transistors used therefor. If the Vgs voltage is less than the threshold voltage of the PMOS transistors, then the gate of the power transistor M
11
is no longer precharged, so that the transistor M
11
does not remain in the on state and the pump fails.
A second problem arises when the pump is spontaneously discharged to zero volts by a discharging element at the output of the circuit. This is because charges then remain on the gates of the power transistors M
1
x, and cause a relatively high negative or positive potential there. The consequence of this is that all the power transistors M
1
x are greatly turned on and connect the input of the pump circuit to its output. If the supply voltage is too low, after the pump has been switched on again, the charges on the gates of the power transistors can no longer be removed. This means that the short circuit between the input and the output of the charge pump is maintained and the pump can no longer run up.
Finally, a third problem occurs by virtue of the fact that the NMOS or PMOS transistors, with their bulk terminal (p-type or n-type well), must be kept at zero volts or be per se at zero volts, in order that the we
Cunningham Terry D.
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
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