Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-02-05
2003-05-06
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185230, C365S226000, C327S536000
Reexamination Certificate
active
06560145
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a charge pump for a memory device, and more particularly relates to a charge pump for a nonvolatile memory with read voltage regulation in the presence of address skew and to a memory device comprising such a charge pump.
2. Description of the Related Art
As is known, the most recent research in nonvolatile memories, in particular EPROM and FLASH memories, is aimed, on the one hand, at achieving increasingly higher data-storage capacities, and, on the other, at producing memories that are able to operate at low supply voltages to meet the ever-increasing demand for lower consumption typical of portable devices, such as cellphones, digital photocameras, MP3 readers, smart cards, etc., or of consumer electronics.
It is therefore necessary to supply, to the gate terminals of the memory cells, read voltages that are typically higher than the single supply voltage supplied from outside to the memory in order to guarantee a correct reading of the memory cells in any situation.
The read voltages are currently obtained by means of charge pumps having the purpose of boosting the single supply voltage supplied from outside to the memory by an amount such as to reach the read voltage necessary for supplying a sufficient read current to the memory cells.
BRIEF SUMMARY OF THE INVENTION
By way of example,
FIG. 1
shows the circuit diagram of a nonvolatile memory using a charge pump according to the prior art. In particular, in
FIG. 1
only the parts of the nonvolatile memory that are useful for understanding the present invention are shown.
As illustrated in
FIG. 1
, the nonvolatile memory, designated as a whole by
1
, comprises a row predecoder stage
2
receiving, via an input buffer
4
, the addresses ADD supplied to the memory
1
, and a row decoder stage
6
cascade-connected to the row predecoder stage
2
and having a plurality of outputs connected to respective word lines
8
of a memory array
10
, and on which respective biasing voltages for the word lines
8
are supplied.
The nonvolatile memory
1
further comprises a charge pump
12
having a supply input connected to a supply line
14
set at a supply voltage V
CC
(typically 2.7-3.8 V) supplied from outside to the memory
1
, and an output supplying a read voltage V
READ
higher than the supply voltage V
CC
, which is then supplied to an input of the row decoder stage
6
, which uses it for biasing the word lines
8
during the step of reading of the data stored in the memory array
10
.
The charge pump
12
comprises a voltage boosting circuit
16
receiving on an input the supply voltage V
CC
and supplying on an output the read voltage V
READ
, and is formed by a plurality of booster stages
18
cascaded together between the input and the output of the charge pump
12
.
In particular, the booster stages
18
are of the so-called Dickson type, and are implemented by means of a MOS transistor-boosting capacitor pair and a MOS transistor-pumping capacitor pair appropriately connected together.
Charge transfer from one boosting stage
18
to the next towards the output is via commands from mutually complementary logic-type phase signals, in the example illustrated in
FIG. 1
four phase signals designated by A, B, C, D, which are supplied to inputs of the booster stages
18
and are generated by a phase generating circuit
20
, which is a logic circuit of a generally known type, and comprises a clock generator stage
22
basically formed by an oscillator supplying on an output a clock signal CK having a pre-set frequency, and a non-overlapping signal generator stage
24
receiving on an input the clock signal CK supplied by the clock generator stage
22
, and supplying on outputs the phase signals A, B, C, D, which are then supplied to the booster stages
8
.
Finally, the charge pump
12
comprises a regulator circuit
26
receiving on inputs the read voltage V
READ
and a reference voltage V
REF0
, and supplying on an output a logic-type regulation signal STOP assuming a first logic level, for example a high level, when the read voltage V
READ
is higher than or equal to the reference voltage V
REF0
, and a second logic level, low in the example considered, when the read voltage V
READ
is smaller than the reference voltage V
REF0
.
The regulation signal STOP is then supplied to an input of the non-overlapping signal generator stage
24
to interrupt supply of the phase signals A, B, C, D to the booster stages
8
when the read voltage V
READ
exceeds the reference voltage V
REF0
, in order to prevent malfunctioning of the memory
1
, such as phenomena of soft-programming or soft-erasing of the memory cells caused by too high read voltages.
FIG. 2
shows the voltage-current characteristic of the charge pump
12
of FIG.
1
. As may be noted, the charge pump
12
is able to supply read voltages V
READ
having a value that is substantially constant and is equal to the reference voltage V
REF0
(Approximately 4.5-5 V) for supplied currents of between zero and a value I
0
of the order of mA, and for currents higher than I
0
, values decreasing down to a value equal to that of the supply voltage V
CC
when the current supplied by the charge pump
12
assumes its maximum value I
MAX0
.
It is moreover known that one of the specifications of nonvolatile memories is that they must guarantee the user correct reading of the data as long as the time elapsing between the supply of two successive addresses to the input of the memory is longer than, or at the most equal to, the memory access time, i.e., in other words, as long as the address transition frequency at the input of the memory is lower than, or at the most equal to, the inverse of the memory access time, which, as is known, is defined as the time elapsing between the instant at which an address is supplied in a stable way to the input of the memory and the instant at which the content of the said address is available on the output of the memory.
Consequently, to guarantee compliance with the specifications regarding reading times, charge pumps are sized in such a way as to be able to meet the maximum current requirement by the decoding circuitry to which they are connected as long as the addresses vary at a frequency lower than, or at the most equal to, the inverse of the memory access time, in such a way as to guarantee that the read voltage V
READ
will remain constant at the aforesaid value V
REF0
over the entire memory operation range.
In particular, the current required from the charge pump by the decoding circuitry is not constant but is proportional to the frequency at which the addresses at the input of the memory vary, and presents a pulse pattern with peaks in correspondence of the transitions of the addresses and a mean value that may be expressed by the following relation: I∝f
ADD
C
DEC
·V
READ
, namely, a mean value that is a function of the address transition frequency f
ADD
, of the read voltage V
READ
, and of the overall capacitance C
DEC
“seen” by the row decoder. It assumes its maximum value when the row decoder “sees” the maximum capacitance.
The maximum voltage V
MAX
that the pump charge can theoretically supply when the current requirement is zero is V
MAX
=(n+1)·V
CC
>V
REF0
, where n is the number of booster stages forming the charge pump, whereas the maximum current I
MAX0
that may be supplied by the charge pump when its output voltage is equal to the supply voltage V
CC
can, instead, be expressed by the following relation: I
MAX0
=f
CK
·C
P
·V
CC
. Namely, it is equal to the product of the supply voltage V
CC
, the charge pump capacitance C
P
, and the frequency f
CK
of the clock signal supplied to the non-overlapping signal generator which generates the phases supplied to the booster stages.
The frequency of the clock signal CK, starting from which the phases of a charge pump are generated, is thus determined in the memory design phase, according, among other things, to the number of booster stages forming the charge pump and t
Buono Luigi
Martines Ignazio
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