Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-12-28
2004-07-20
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S535000, C327S536000
Reexamination Certificate
active
06765428
ABSTRACT:
RELATED APPLICATION
The present application claims the benefit of Korean Patent Application No. 87289/2000 filed Dec. 30, 2000, which is herein fully incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit for generating a boosted voltage in a semiconductor memory, and more particularly, to a charge pump circuit in a semiconductor memory.
2. Discussion of the Related Art
FIG. 1
shows a block diagram of a charge pump device or circuit
50
in a semiconductor memory according to a related art.
Referring to
FIG. 1
, the charge pump circuit
50
is constructed with a level detector
10
for detecting a level of a boosted voltage VPP by comparing it with a reference voltage VREF and producing a level detection signal DET based on the comparison results, an oscillator
20
for producing a pulse signal PUL in accordance with the level detection signal DET output from the level detector
10
, and a charge pump unit
30
for outputting a boosted voltage VPP by carrying out a charge pumping operation in accordance with the pulse signal PUL output from the oscillator
20
. The charge pump unit
30
comprises at least one of a plurality of unit charge pumps
30
-
1
to
30
-
n.
FIG. 2
is a detailed circuit diagram of the level detector
10
in FIG.
1
. As shown in
FIG. 2
, the level detector
10
is constructed with a differential amplifier for comparing the boosted voltage VPP to the reference voltage VREF and outputting the level detection signal DET. A pumping enabling signal PUMP_ON is input to a gate of an NMOS transistor NM
3
.
The operation of the above-constructed charge pump circuit
50
in a semiconductor memory according to a related art is explained in detail as follows.
When the charge pump circuit
50
is operated by a high level stage of the pumping enabling signal PUMP_ON, the level detector
10
detects a level of the boosted voltage VPP by comparing a VPP level to the reference voltage VREF. Namely, as shown in
FIG. 2
, if the level of the reference voltage VREF is higher than the level of the boosted voltage VPP, the level detector
10
outputs a level detection signal DET of a high level through an inverter INV. If the level of the reference voltage VREF is lower than the level of the boosted voltage VPP, a level detection signal DET of a low level is output by the level detector
10
.
The oscillator
20
operates based on the level detection signal DET output from the level detector
10
to initiate or stop the operation of the unit charge pumps
30
-
1
to
30
-
n
of the charge pump unit
30
. Namely, when the level detection signal DET output from the level detector
10
is at a high level, the VPP level is increased by operating all the unit charge pumps
30
-
1
to
30
-
n
of the charge pump unit
30
. If the level detection signal DET output from the level detector
10
is at a low level, the VPP level is decreased by stopping the operation of all the unit charge pumps
30
-
1
to
30
-
n.
In this regard, the charge pump circuit of the related art carries out the pumping operation by operating the plurality of the unit charge pumps at once without any regard to whether the device is in a low or high speed operation (low or high power consumption). This results in excessive power consumption by the device since operating all unit charge pumps, even if it is unnecessary, requires a significant amount of energy.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a charge pump circuit or device in a semiconductor memory that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a charge pump circuit or device in a semiconductor memory for reducing power consumption by driving selectively a plurality of unit charge pumps in accordance with required power amounts.
Another object of the present invention is to provide a charge pump device and method that is efficient and effective in its operation.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a charge pump circuit in a semiconductor memory according to an embodiment of the present invention, includes a charge pump unit constructed with a first to an nth unit charge pumps, a multi-level detector detecting a level of a boosted voltage by multi-steps so as to drive the unit charge pumps variably in accordance with an amount of power consumption of the device, an oscillator producing a pulse signal in accordance with a detect signal of the multi-level detector, and a logic operation part operating the pulse signal of the oscillator and a level detect signal produced from the multi-level detector and outputting the operated signal to the charge pump unit.
Preferably, the multi-level detector includes a voltage distributor dividing a power source voltage into a first to an nth voltage levels, and a first to an nth level detectors detecting the level of the boosted voltage by comparing the boosted voltage to the first to nth voltage levels divided by the voltage distributor.
More preferably, the first unit charge pump is always driven by the detection signal output from the multi-level detector, all of the first to nth unit charge pumps are driven when power is on or the amount of the power consumption is large, and the second unit charge pump is driven when the power consumption is small on an active stage.
In another aspect of the present invention, a charge pump circuit in a semiconductor memory includes a charge pump unit constructed with a first to an nth unit charge pumps, a multi-level detector detecting a level of a boosted voltage by multi-steps so as to drive the unit charge pumps variably in accordance with an amount of power consumption of the device, an oscillator producing a pulse signal in accordance with a detect signal of the multi-level detector, and a logic operation part operating the pulse signal of the oscillator and a level detection signal produced from the multi-level detector, the logic operation part outputting the operated signal to the first to nth unit charge pumps, wherein the multi-level detector comprises a voltage distributor dividing a power source voltage into a first to an nth voltage levels, and a first to an nth level detectors detecting a plurality of levels of the boosted voltage by comparing the boosted voltage to the first to nth voltage levels divided by the voltage distributor.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5982222 (1999-11-01), Kyung
patent: 6128242 (2000-10-01), Banba et al.
patent: 6370075 (2002-04-01), Haeberli et al.
Kim Sun Min
Park Jong-Hoon
Birch & Stewart Kolasch & Birch, LLP
Hynix / Semiconductor Inc.
Lam Tuan T.
Nguyen Hiep
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