Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
2002-02-05
2004-05-11
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S216000, C257S235000, C257S241000
Reexamination Certificate
active
06734475
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a charge pump semiconductor device of large current output used for a power source circuit, etc., particularly to the charge pump semiconductor device enabling to operate stably by preventing occurrence of pseudo latch-up.
2. Description of the Related Art
Recent picture instruments such as video camera, digital still camera (DSC), DSC phone, etc. use CCD (Charge Coupled Devices) to take in the picture. A CCD driving circuit for driving the CCD needs a power source circuit of high voltage (in or around a range of 10 to 20 V) of positive and negative and large current (several mA). Nowadays, the high voltage is generated using a switching regulator.
The switching regulator can generate high voltage with high performance, that is, high power efficiency (output power/input power). However, the circuit has a demerit generating harmonic noise at switching of current so as to use shielding the power source circuit. Further needs a coil as external parts.
Then, Dickson charge pump device is noticed as the above-mentioned power source circuit for portable equipment. The circuit is described in detail in technical literature: John F. Dickson “On-chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-11, NO. 3 pp. 374-378 JUNE 1976.
A circuit diagram of four stages Dickson charge pump device is shown in FIG.
5
. Diodes D
1
to D
5
are connected in series. Symbols C to C
4
are coupling capacitors connected to connected points of each of the diodes D
1
to D
5
, symbol CL is an output capacitor, and symbols CLK and CLKB are input clock pulses being opposite phase each other. Symbol
51
is a clock driver receiving CLK and CLKB, and symbol
52
is a current load. Power source voltage Vdd is supplied to the clock driver
51
. Thus, output amplitude of clock pulses &phgr;1 and &phgr;2 output from the clock driver
51
becomes almost Vdd. The clock pulse &phgr;1 is supplied to the capacitors C
2
and C
4
, and the clock pulse &phgr;2 is supplied to the capacitors C
1
and C
3
.
In the stable state, when constant current Iout flows through output, input current to the charge pump device is current from input voltage Vin and current supplied from the clock driver. These currents are the followings, if ignoring charge/discharge current to stray capacitor. Average current of 2Iout flows to arrow direction of a solid line while &phgr;1=High and &phgr;2=Low.
Average current of 2Iout flows to arrow direction of a dotted line while &phgr;1=Low and &phgr;2=High. These average currents at clock cycle become Iout all. Boosted voltage Vout of the charge pump device at stable state is expressed as the following:
V
out
=V
in
−V
d
+n
(
V
&phgr;′
−V
I
−V
d
) (1)
Here, V
&phgr;′
is voltage amplitude generated by coupling capacitor caused by change of the clock pulse. VI is voltage fall generated by output current Iout, and Vin is input voltage, it is usually power source voltage Vdd in positive boosting and 0 V in negative boosting. V
d
is forward bias diode voltage, and n is numbers of stages of pumping. Further, V
I
and V
&phgr;′
are expressed as the followings:
V
I
=I
out
/f
(
C+C
s
)=(2
I
out
T/
2)/(
C+C
s
) (2)
V
&phgr;′
=V
&phgr;
C
/(
C+C
s
) (3)
Here, C
1
to C
4
are clock-coupling capacitors, C
s
is stray capacitor at each node, V
&phgr;
is clock pulse amplitude, f is frequency of clock pulse, and T is clock period. Power efficiency of the charge pump is expressed by the following equation, placing Vin=Vdd, and neglecting charge/discharge current flowing to the stray capacitor from the clock driver.
&eegr;=
V
out
I
out
/(
n+
1)
V
dd
I
out
=V
out
/(
n+
1)
V
dd
(4)
Thus, in the charge pump device, boosting is carried out by transferring electric charge to the next stage one after another using diodes as a charge transfer device. However, considering attaching to semiconductor integrated circuit device, using MOS transistor is realized easier than diode of PN junction in view of the adaptation to the process.
Then, use of MOS transistor is proposed instead of diode for the charge transfer device. In this case, threshold voltage Vth of MOS transistor displaces Vd in the equation (1).
However, enough examination has not been carried out about device construction for assembling the charge pump device in the semiconductor integrated circuit device and realizing large current and stable operation in the present circumstances. Particularly, in charge pump device of large output current, there is a problem that latch-up appears at starting operation, however the mechanism has not been made clear.
SUMMARY OF THE INVENTION
The invention is carried out in view of the above-mentioned conventional technical problem, an object thereof is to realize a charge pump device of large current and high efficiency. Further another object is to prevent occurrence of latch-up not avoiding with the conventional charge pump device of large current and to realize stable operation.
The charge pump device of the invention provides: plurality of well regions formed on a substrate separately each other; plurality of charge transfer transistors formed individually in each of said well regions and connected in series each other; and capacitors coupled to each connecting point of these charge transfer transistors, wherein drain layer of said charge transfer transistor and said well region in which the charge transfer transistor is formed are connected electrically.
According to the characteristic constitution of the invention, the well regions in which the charge transfer transistors are formed are separated each other, and drain layer of the charge transfer transistor and well region in which the charge transfer transistor is formed are connected electrically. That is, since relation “voltage between gate and substrate Vgb=voltage between gate and drain Vgd” is held, increase of threshold voltage Vth of the charge transfer transistor by back gate bias effect is prevented. Thus, since ON resistance of the charge transfer transistor decreases, a charge pump device of large output current can be realized.
Further, in order to realize the above-mentioned characteristic constitution connecting electrically the drain layer of the charge transfer transistor and the well region in which the charge transfer transistor is formed, high concentration diffusion layer being same conductivity type as the well region is formed in the well region, and the diffusion layer and said drain layer are connected. Thus, since the drain layer of the charge transfer transistor and the well region in which the charge transfer transistor is formed are connected electrically with low resistance, increase of threshold voltage Vth of the charge transfer transistor by back gate bias effect is surely prevented.
Although the charge pump device of large output current can be realized by the above way according to the characteristic constitution of the invention, there is a problem that latch-up generates easily at operation starting. Then another characteristic constitution of the invention separates electrically said well regions in which said charge transfer transistors are formed so that parasitic thyristor construction causing pseudo latch-up is not formed.
The concrete characteristic constitution is that drain layer of said charge transfer transistor and said first conductive type well region in which the charge transfer transistor is formed are connected electrically, each first conductive type well region in which said charge transfer transistor is formed is included by a second conductive type well region, and the adjacent said second conductive type well regions are separated.
That is, each charge transfer transistor is formed in double well regions (first conductive type
Myono Takao
Uemoto Akira
Fenty Jesse A.
Fish & Richardson P.C.
Jackson Jerome
Sanyo Electric Co,. Ltd.
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