Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2002-09-04
2004-08-24
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S536000, C363S060000
Reexamination Certificate
active
06781440
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a voltage generating circuit, and more particular to a charge pump circuit with a voltage multiplier for boosting a clock signal to generate higher output voltages.
BACKGROUND OF THE INVENTION
Charge pump circuit is used for generating a higher output voltage when inputting a voltage regularly, and they have been used in non-volatile memory, such as EEPROM (Electrically Erasable Programmable Read-Only Memory) and flash memory, for programming and erasing operations through their floating gates. Thus, the flash memory can finish three kinds of basic operations, in another word, reading (a byte or word), writing (a byte or word), and erasing (a byte or word) operations.
Please refer to FIG.
1
. FIG
1
shows a conventional four-stage Dickson charge pump circuit. As shown in
FIG. 1
, the charge pump circuit
100
includes four voltage-boosting stages
101
,
102
,
103
, and
104
connected series between an input node
105
and an output node
109
. Voltage-boosting stages
101
,
102
,
103
, and
104
have supply terminals, control terminals
110
,
111
,
112
, and
113
, and output terminals respectively. Also, the voltage-boosting stages form three voltage nodes
106
,
107
, and
108
respectively for coupling to each other. Each voltage-boosting stage
101
,
102
,
103
, and
104
includes a MOS (Metal-Oxide-Semiconductor) transistor which has a gate terminal for coupling to its drain terminal to form a diode-coupled transistor
118
,
119
,
120
, and
121
respectively. In the Dickson charge pump circuit
100
, the voltage-boosting stage
101
includes a capacitor
114
that one terminal of the capacitor
114
is the control terminal
110
for receiving a clock signal CLK, and other terminal thereof is coupled to the input node
105
. The voltage-boosting stage
102
includes a capacitor
115
that one terminal of the capacitor
115
is the control terminal
111
for receiving an inverse signal {overscore (CLK)} of the clock signal CLK, and the other terminal thereof is coupled to the input node
106
. The voltage-boosting stage
103
includes a capacitor
116
that one terminal of the capacitor
116
is the control terminal
112
for receiving the clock signal CLK, and the other terminal thereof is coupled to the input node
107
. The voltage-boosting stage
104
includes a capacitor
117
that one terminal of the capacitor
117
is the control terminal
113
for receiving the inverse signal {overscore (CLK)} of the clock signal CLK, and the other terminal thereof is coupled to the input node
108
. Then, the diode-coupled transistor
118
operates as an unidirectional switch to transfer the charge stored on the capacitor
114
to the capacitor
115
. Also, the diode-coupled transistor
119
operates as an unidirectional switch to transfer the charge stored on the capacitor
115
to the capacitor
116
, the diode-coupled transistor
120
operates as an unidirectional switch to transfer the charge stored on the capacitor
116
to the capacitor
117
, and the diode-coupled transistor
121
operates as an unidirectional switch to transfer the charge stored on the capacitor
117
to an output capacitor C
out
.
The Dickson charge pump circuit
100
further includes a diode-coupled transistor
122
. The diode-coupled transistor
122
is coupled between an input voltage V
DD
and the input node
105
and is also operated as a unidirectional switch to transfer the charge of the input voltage V
DD
to the capacitor
114
.
However, the transformation of the charge is decided by a voltage difference between the supply terminal and the output terminal in the voltage-boosting stage. If the voltage difference is higher than a threshold voltage of the diode-coupled transistor, the charge can be transferred. Moreover, the Dickson charge pump circuit utilizes the clock signal CLK and the inverse signal {overscore (CLK)} of the clock signal CLK to increase the voltage in the node. In an n-stage Dickson charge pump circuit, an output voltage V
out
can be obtained by
V
out
=
V
DD
+
Δ
V
-
∑
k
=
1
n
V
th
(
V
k
)
Δ
V
=
V
DD
C
C
+
C
s
-
I
out
f
(
C
+
C
s
)
Where V
DD
is a logic high voltage value of the clock signal, V
th
is a threshold voltage of each MOS, C is a capacitance of each voltage-boosting stage's capacitor, C
s
is a stray capacitance at each node, f is a frequency of the clock signal, and I
out
is an output current loading.
Hence the necessary condition for the charge pump circuit to work is &Dgr;V>V
th
.
However, because the body effect of the transistor increases the threshold voltage and the input voltage is lower than 1.8 V, the clock signal cannot increase a sufficient voltage at the node to overcome the threshold voltage.
Because of the technical defects described above, the applicant keeps on carving unflaggingly to develop “charge pump circuit with voltage multiplier for boosting clock signal and method thereof” through wholehearted experience and research.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a charge pump circuit with a voltage multiplier for boosting a clock signal and a method thereof.
It is another object of the present invention to provide a charge pump circuit that includes a plurality of voltage-boosting stages and a plurality of voltage multipliers.
It is further another object of the present invention to provide the voltage multipliers for boosting a clock signal to amplify a voltage at each connecting node between a plurality of voltage-boosting stages and provide a stable output voltage.
The present invention provides a charge pump circuit that includes a plurality of voltage-boosting stages connected in series with each other and each of which has a supply terminal, a control terminal, and an output terminal respectively, and a plurality of voltage multipliers, each of which has an input terminal, a first output terminal for outputting a first clock signal, and a second output terminal for outputting a second clock signal, a magnitude of the first clock signal is a multiple of that of the second clock signal, the second output terminal of a respective one of the voltage multipliers excluding a last one thereof is coupled to the input terminal of a downstream voltage multiplier, and the first output terminal of a respective one of the voltage multipliers is coupled to the control terminal of a respective one of the voltage-boosting stages.
Preferably, the first clock signal and the respective clock signal, coupled to the respective voltage multiplier, are two out-of-phase signals.
Preferably, the second clock signal and the respective clock signal, coupled to the respective voltage multiplier, are two out-of-phase signals.
Preferably, the voltage-boosting stage stages includes a switching circuit having a first signal terminal, a second signal terminal, and a control terminal, wherein the second signal terminal is coupled to the first signal terminal of a downstream the switching circuit, and an energy storage circuit having a first terminal coupled to the second signal terminal and a second terminal as the control terminal of the voltage-boosting stage.
Certainly, the switching circuit includes an N-Type MOS (Metal-Oxide-Semiconductor) transistor.
Certainly, the energy storage circuit includes a capacitor.
Preferably, each stage of the plurality of voltage-boosting stages includes a MOS transistor having a gate coupled to a drain for forming a diode-coupled transistor.
Preferably, each of the voltage multipliers is a voltage doubler.
Preferably, each of the voltage multipliers includes an inverting amplifier having an input terminal as the input terminal of the voltage multiplier and an output terminal as the second output terminal of the voltage multiplier, a first P-type MOS transistor having a gate terminal, a first conducting terminal, and a second conducting terminal, wherein the first conducting terminal is coupled to a power source, a second P-typ
Englund Terry L.
Volpe and Koenig P.C.
Winbond Electronics Corp.
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