Charge pump circuit with reduced parasitic capacitance

Details Charge pump circuit with reduced parasitic capacitance Charge pump circuit with reduced parasitic capacitance

2007-10-29

2008-10-21

Pert, Evan (Department: 2826)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

07439795

ABSTRACT:
A charge pump circuit is provided with a capacitor for generating a boosted voltage from a power supply voltage in response to a clock signal; and an output node from which the boosted voltage is externally outputted. The capacitor includes a first well formed within a substrate, a second well formed within the first well, first and second diffusion regions formed within the second well to receive the clock signal, a channel region provided between the first and second diffusion regions in which channel region a channel is formed in response to the clock signal; and an electrode positioned over the channel region across a dielectric and connected with the output node. The output node is also connected with the first well to apply said boosted voltage to the first well.

REFERENCES:
patent: 5081371 (1992-01-01), Wong
patent: 5828095 (1998-10-01), Merritt
patent: 9-266281 (1997-10-01), None

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