Charge pump circuit with latch-up prevention

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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C327S535000, C363S060000

Reexamination Certificate

active

11017854

ABSTRACT:
In an embodiment of the invention, a charge pump circuit has a latch-up prevention circuit. The latch-up prevention circuit has a depletion P-channel MOS transistor and a resistor serially connected with each other between a negative output terminal and a ground terminal. A first bidirectional PNP-transistor is connected between a back gate of the depletion MOS transistor and the ground terminal. A second bidirectional PNP-transistor is connected between the back gate of the depletion MOS transistor and the negative output terminal. A third bidirectional PNP-transistor is between the ends of the resistor to bypass it. The base of the first bidirectional PNP-transistor is connected to the negative output terminal, the gate of the depletion MOS transistor and the bases of the second and third bidirectional PNP-transistors are connected to the ground terminal.

REFERENCES:
patent: 4797899 (1989-01-01), Fuller et al.
patent: 5640123 (1997-06-01), Akaogi et al.
patent: 5917354 (1999-06-01), Nakai et al.
patent: 5942932 (1999-08-01), Shen
patent: 6741118 (2004-05-01), Uchikoba et al.
patent: 7031219 (2006-04-01), Hsu et al.
patent: 6-165482 (1994-06-01), None

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