Charge pump circuit with exponetral multiplication

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

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327390, 327346, 307110, 363 60, H02M 318

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active

054365872

ABSTRACT:
A charge pump circuit comprises a plurality of voltage doubler circuits connected together such that a first voltage output generated by a first portion of a kth one of the voltage doubler circuits is substantially equal to Vdd*2.sup.k and Vdd*2.sup.k-1) on odd and even phases, respectively, of a first clock signal, and a second voltage output generated by a second portion of the kth one of the voltage doubler circuits is substantially equal to Vdd*2.sup.k-1) and Vdd*2.sup.k on the odd and even phases, respectively, of the first clock signal. Each of the voltage doubler circuits is constructed such that when its first portion is providing a voltage of Vdd*2.sup.k and a current to a next stage, its second portion is recharging a capacitor in that portion to Vdd*2.sup.k-1), and when its second portion is providing a voltage of Vdd*2.sup.2 and a current to the next stage, its first portion is recharging a capacitor in that portion to Vdd*2.sup.k-1). An output circuit is connected to a last one of the voltage doubler circuits to provide other circuitry with a substantially constant output voltage Vpp and output current Ipp, by providing such voltage and current from a first voltage output of the last voltage doubler circuit on odd phases of the first clock signal, and from a second voltage output of the last voltage doubler circuit on even phases of the first clock signal.

REFERENCES:
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patent: 4149232 (1979-04-01), Eaton, Jr.
patent: 4271461 (1981-06-01), Hoffmann et al.
patent: 4511811 (1985-04-01), Gupta
patent: 4638464 (1987-01-01), Cranford, Jr. et al.
patent: 4673829 (1987-06-01), Gupta
patent: 4769753 (1988-09-01), Knudson et al.
Dickson, J. F., "On-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique," IEEE Journal of Solid-State Circuits, vol. SC-11, No. 3, pp. 374-378 (1976).

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