Charge pump circuit with bypass transistor

Details Charge pump circuit with bypass transistor Charge pump circuit with bypass transistor

1999-10-15

2002-04-16

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S537000

Reexamination Certificate

active

06373322

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to a voltage conversion circuit, and more particularly, to a voltage conversion circuit including a charge pump circuit for boosting an input voltage.
There is a practice in the prior art that whenever a semiconductor memory, such as a DRAM, is not in use, an external supply voltage which has a lower than normal level is provided to the semiconductor memory, thus switching the voltage supply to a low voltage mode. In the low voltage mode, an external supply voltage of a level which is sufficient to enable a refresh operation for maintaining stored information is used, thus reducing the power dissipation of the semiconductor memory.
A semiconductor memory is generally provided with a voltage conversion circuit which boosts an external supply voltage to supply various internal circuits with a boosted voltage or voltages. For example, such a voltage conversion circuit boosts an external supply voltage of 3.3 volts, which is supplied during a normal voltage mode, to a voltage range from 4.5 to 4.8 volts or boosts an external supply voltage of 2.0 volts, which is supplied during a low voltage mode, to a voltage range from 3.5 to 3.8 volts.
A conventional charge pump circuit
100
as shown in
FIG. 1
is extensively employed as a voltage conversion circuit.
Referring to
FIG. 1
, the charge pump circuit
100
comprises first and second booster stages
1
,
2
, first and second inverter circuits
3
,
4
, first, second and third gate transistors T
1
, T
2
, T
3
and a stabilizing capacitive element C
0
. The first booster stage
1
is connected to an external supply voltage Vcc via the first gate transistor T
1
which is formed by an NMOS transistor. The second transistor T
2
which is formed by a PMOS transistor is connected between the first booster stage
1
and the second booster stage
2
. The second booster stage
2
is connected to an internal bus which supplies a voltage Vout to various circuits via the third gate transistor T
3
formed by a PMOS transistor.
The first booster stage
1
comprises a first capacitive element C
1
which has a first terminal connected to the source terminals of the first and second gate transistors T
1
, T
2
and a second terminal connected to the output terminal of the first inverter circuit
3
which is formed by a CMOS transistor. The second booster stage
2
comprises a second capacitive element C
2
which has a first terminal connected to the drain terminal of the second gate transistor T
2
and to the source terminal of the third gate transistor T
3
and which also has a second terminal connected to the output terminal of the second inverter circuit
4
which is formed by a CMOS transistor. The stabilizing capacitive element C
0
has a first terminal connected to the internal bus and a second terminal connected to ground, but which may alternatively be connected to the external supply voltage Vcc.
When the first inverter circuit
3
delivers an L level (0 volt) signal, the first capacitive element C
1
is charged in response to the turn-on of the first gate transistor T
1
and the turn-off of the second gate transistor T
2
. The potential at the first terminal of the capacitive element C
1
then rises to the external supply voltage Vcc.
Subsequently when the first inverter circuit
3
delivers an H level (positive &agr; volt) signal when the first gate transistor T
1
is off, the potential at the first terminal of the first capacitive element C
1
rises to a primary boosted voltage V
1
which is equal to Vcc+&agr;, where “&agr;” represents the external supply voltage Vcc. Thus, the first inverter circuit
3
operates on the external supply voltage Vcc, which is then supplied as an H level signal to the first capacitive element C
1
.
When the second inverter circuit
4
delivers an L level signal when the third gate transistor T
3
is off, the second capacitive element C
2
is charged in response to the turn-on of the second gate transistor T
2
, and the potential at the first terminal of the capacitive element C
2
rises to the primary boosted voltage V
1
which is equal to Vcc+&agr;.
Subsequently, when the second inverter circuit
4
delivers an H level (positive &agr;) signal when the second gate transistor T
2
is off, the potential at the first terminal of the second capacitive element C
2
rises to a secondary boosted voltage V
2
which has the predetermined voltage &agr; added to the primary boosted voltage or V
1
+&agr;=Vcc+2&agr;. The second inverter circuit
4
also operates on the external supply voltage Vcc, which is then supplied as an H level signal to the second capacitive element C
2
.
Subsequently, when the third gate transistor T
3
is turned on, the secondary boosted voltage V
2
which has charged the second capacitive element C
2
is supplied to various internal circuits as an internal bus voltage Vout. Thus, the charge pump circuit
100
produces the internal bus voltage Vout by boosting the external supply voltage Vcc by 2&agr;. By repeating the described boosting operation, the charge is stored across the stabilizing capacitive element C
0
to raise the potential of the internal bus voltage source Vout.
It is to be noted, however, that the external supply voltage Vcc supplied to the charge pump circuit
100
has different levels between the normal voltage mode and the low voltage mode. The charge pump circuit
100
has a boosting efficiency which changes greatly with a variation in the external supply voltage Vcc. The lower the external supply voltage Vcc, the more rapidly the booster efficiency is degraded. Circuit parameters (capacitances of the first and second capacitive elements C
1
, C
2
) of the charge pump circuit
100
are chosen on the basis of the low voltage mode so that no difficulty is caused by an insufficient booster efficiency which prevails in the low voltage mode.
However, when the circuit parameters of the charge pump circuit
100
are chosen on the basis of the low voltage mode, an excessive booster capability results when the external supply voltage is high as in the normal voltage mode which is assumed during a read/write operation, causing an undesirable increase in the power dissipation.
To reduce the power dissipation in the normal voltage mode, the second and third gate transistors T
2
, T
3
are turned on simultaneously after the first booster stage
1
has produced the primary boosted voltage V
1
, thus effecting a single stage booster pumping, which means delivering the primary boosted voltage V
1
as the internal bus voltage Vout, rather than boosting the primary boosted voltage in the second booster stage
2
while maintaining an output from the second inverter circuit
4
at its L level. In contrast to the single stage booster pumping, the term “two stage booster pumping” refers to combining the booster operations in both the first and second booster stages
1
,
2
to deliver the secondary boosted voltage V
2
as the internal bus voltage Vout.
In the single stage booster pumping, the primary boosted voltage V
1
produced by the first booster stage
1
is delivered as the internal bus voltage Vout via the second and third gate transistors T
2
, T
3
. Thus, a flow of the charge via the second and third gate transistors T
2
, T
3
produces a voltage drop or a current drop therein, resulting in a decrease in the booster efficiency. More specifically, the second and third gate transistors T
2
, T
3
are formed by PMOS transistors, which do not produce a voltage drop across their sources and drains in a d.c. operation. However, because the transistors T
2
, T
3
are connected in series, they exhibit an increased effective channel length. This prevents the charge discharged from the first capacitive element C
1
in an a.c. operation from being delivered in its entirety from the third gate transistor T
3
, causing a voltage drop or a reduction in the booster efficiency. The booster efficiency of the charge pump circuit
100
is also degraded by an unnecessary charging of the second capacitive element C
2
. The same is

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