Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-12-08
2001-03-06
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S534000, C327S537000
Reexamination Certificate
active
06198342
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a charge pump circuit for generating, for example, write voltage or erase voltage or the like in nonvolatile semiconductor storage devices by boosting or lowering the power supply voltage.
For next-generation flash memories, there is a demand for further lower voltage, smaller power and lower cost (downsizing of circuits) than today's counterparts. In particular, charge pump circuits for generating a high voltage required to write or erase data into or from memory cells occupy a large portion of the chip area, and therefore it is important to implement the size reduction.
The charge pump circuit is a circuit for generating a voltage, or a negative voltage, higher than a power supply voltage by boosting or lowering the power supply voltage. A charge pump for generating a negative voltage to be used for block erasure in NOR flash memories (hereinafter, referred to as negative-voltage charge pump) generates a negative voltage of about −11 V from a power supply voltage (3 V or 5 V). However, with the circuit structure of conventional negative-voltage charge pumps, the circuit would necessarily be upsized acceleratively to obtain the same output from further lower power supply voltages with a view to the voltage reduction, which has been an obstacle to cost reduction.
Conventionally, as one of the circuit structure of the negative-voltage charge pump circuit, there has been a method in which a circuit part for fall of voltage is made up of P-channel transistors. Below given are a brief description of this negative-voltage charge pump using P-channel transistors as well as problems involved in the case where P-channel transistors are used.
An example of the negative-voltage charge pump circuit using P-channel transistors is shown in FIG.
11
. In the figure, a portion surrounded by broken line is a pump cell
1
that serves as a basic unit of a charge pump, and a negative-voltage charge pump circuit is made up by connecting several pump cells
1
in series.
Clocks clk
1
-clk
4
as shown in
FIG. 12
are inputted to individual clock input terminals CLK
1
-CLK
4
of the pump cells
1
. More specifically, clocks clk
1
, clk
2
are inputted to the clock input terminals CLK
1
, CLK
2
of the first-stage pump cell
1
, clocks clk
3
, clk
4
are inputted to the clock input terminals CLK
3
, CLK
4
of the second-stage pump cell
1
, and clocks clk
1
, clk
2
are inputted to the clock input terminals CLK
1
, CLK
2
of the third-stage pump cell
1
. Similarly for the following, clocks clk
1
, clk
2
are inputted to the clock input terminals CLK
1
, CLK
2
of pump cells
1
of odd-numbered stages. By contrast, clocks clk
3
, clk
4
which are shifted 180 degrees with respect to the clocks clk
1
, clk
2
are inputted to the clock input terminals CLK
3
, CLK
4
of pump cells
1
of even-numbered stages.
Now the operation of the pump cell
1
is described by taking a stage
2
in
FIG. 11
as an example. Voltage of a node OUT
1
, which is the input of the stage
2
, oscillates at an amplitude of a power supply voltage Vcc generally in synchronization with the clock clk
2
as shown by out
1
in
FIG. 13
, by action of a capacitor C
4
of the preceding stage
1
and the clock clk
2
inputted to this capacitor C
4
. Meanwhile, voltage of a node OUT
2
, which is the output of the stage
2
, oscillates at the amplitude of the power supply voltage Vcc generally in synchronization with the clock clk
4
as shown by out
2
in
FIG. 13
, by action of a capacitor C
6
inside the stage
2
and the clock clk
4
inputted to this capacitor C
6
.
Between the node OUT
1
and the node OUT
2
, is provided a transistor M
7
having a role of transferring charges between the two nodes OUT
1
and OUT
2
. The voltage of a node B in
FIG. 11
, when the clock clk
4
is an “L” with a transistor M
6
conducting, makes a transition at the same voltage as the node OUT
1
as shown by broken line B in FIG.
13
. In contrast to this, when the clock clk
4
is an “H” with the transistor M
6
non-conducting, the voltage makes a transition generally in synchronization with the clock clk
3
by action of a capacitor C
5
connected to the node B and the clock clk
3
inputted to this capacitor C
5
.
Therefore, in the state that the voltage of the node OUT
1
has been pushed down by the capacitor C
4
and that the voltage of the node OUT
2
has been pushed up by the capacitor C
6
, the node B becomes a voltage lower than the source voltage of the transistor M
7
so that the transistor M
7
is opened, allowing the charges to be delivered. Then, in any other state, the transistor M
7
is closed. Therefore, by making up a negative-voltage charge pump by connecting in series the pump cells
1
having the above construction, a negative voltage Vneg can be taken out.
However, the conventional negative-voltage charge pump circuit has the following problems. That is, the negative-voltage charge pump circuit has a capability of lowering the input voltage by an extent of (Vcc-&agr;) (where &agr;>0) per pump cell
1
of one stage. However, the value of &agr; varies from one pump cell
1
to another due to the voltage inside the pump cell
1
. The reason of this is that transfer-use transistors M
5
, M
7
, M
9
are affected by the backgating effect. For a transistor, the larger the voltage difference between its source and well is, the larger the threshold voltage of the transistor becomes due to the backgating effect. In this case, the P-channel transistors constituting the transfer-use transistors M
5
, M
7
, M
9
cannot be made be have their n-well portion voltage lower than the substrate voltage (0 V). Meanwhile, the later stage the pump cells
1
belongs to, the lower the source voltage of the transistors M
5
, M
7
, M
9
becomes. Accordingly, the later the stage in the charge pump is, the larger the voltage difference between source and well becomes so that the influence of the backgating effect increases. That is, if &agr; value of the “i”th-stage pump cell
1
i
is &agr;
i
(i=1, 2, . . . , n), then
0≦&agr;
i
≦&agr;
2
≦ . . . ≦&agr;
n
.
Because voltage reduction of the output voltage per pump cell
1
of one stage becomes smaller in later stages of the charge pump, the number of stages of pump cells
1
needs to be increased proportional to the extent of the voltage reduction. Also, the more the power supply voltage lowers, the more the number of stages of pump cells
1
needs to be increased. Unfortunately, however, increasing the number of stages of pump cells
1
would cause the voltage loss due to the backgating effect to increase proportionally as described above, which in turn gives rise to a need for further increasing the number of stages of pump cells
1
in order to make up for the increased voltage loss. Thus, as a result of voltage reduction of the power supply voltage Vcc, the chip area occupied by the charge pump circuit is increased acceleratively.
Also, when the power supply voltage Vcc is lowered as described above, it can occur that at the “i”th-stage pump cell
1
i
,
Vcc−&agr;
i
<0.
In this case, no matter how many additional pump cells
1
are connected, the voltage of the output voltage Vneg comes not to lower any more. For example, when Vcc=1.8 V, no matter how many additional pump cells
1
are connected, the output Vneg of the negative-voltage charge pump could be no more than −8 V. Therefore, some devise is needed to generate a high voltage or a negative voltage of large absolute value with a low power supply voltage.
As a solution to the above issue that increasing the number of stages of pump cells would cause the voltage loss due to the backgating effect to increase proportionally, there is a method that the amplitude of the clock clk inputted to the pump cell
1
is made larger than the power supply voltage Vcc by some means, thereby reducing the loss due to the backgating effect.
For example, Japanese Patent Laid-Open Publication HEI 6-208798 has proposed a method for enlarging the clock amplitude o
Cunningham Terry D.
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
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