Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2003-05-01
2004-11-02
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S537000, C363S060000
Reexamination Certificate
active
06812773
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to improving the reliability of charge pump circuits, and more specifically to improving the reliability of charge pump circuits by providing means to discharge the gates of field effect transistors between pumping cycles.
(2) Description of the Prior Art
Charge pump circuits are used to generate high voltage in circuits with only low voltage supplies available, such as low voltage flash EEPROM circuits. After the charge pumping operation charge is stored in the internal nodes of the charge pumping circuit which is then discharged into the load. The discharge into a load may not completely discharge the charges stored in the internal nodes resulting in voltage stress on FET gate oxides. This voltage stress can result in a loss of circuit reliability.
U.S. Pat. No. 6,072,358 to Hung et al. describes charge pump circuitry which reduces the voltage stress on transistor gate oxides by biasing the charge pump circuit such that the voltage across the gate oxide is reduced.
U.S. Pat. No. 5,818,289 to Chevallier et al. describes a charge pump circuit which uses a charge transfer switch and associated clocking scheme which reduces the current required to operate the charge pump.
U.S. Pat. No. 5,537,072 to Canclini describes a charge pump circuit which reduces high voltage damage. The switch circuit has a first transistor for conducting current and is controlled by second, third, and fourth transistors. The second transistors protects the first transistor from excessive gate to drain voltage. The third transistor serves as a cascoding transistor protecting the fourth transistor from excessive gate to drain voltage.
SUMMARY OF THE INVENTION
Charge pump circuits are often used to generate high voltages for circuits such as EEPROM circuits. These charge pump circuits usually use FETs in the internal stages of the charge pump circuits. The charge pumping operation stores charge at internal nodes of the circuit to generate the high voltages required. This stored charge produces voltage stress across the FET gate oxide. During the period when the high voltage is delivered to a load the internal nodes are discharged, however often they are not completely discharged leaving continual voltage stress across the FET gate oxides. The reliability of FETs in the charge pump circuits can be degraded by this continual high voltage stress across the FET gate oxides.
It is a principle objective of this invention to provide a method of discharging the internal nodes after current has been delivered to the load, thereby reducing the high voltage stress on the FET gate oxides and improving FET reliability.
It is another principle objective of this invention to provide a circuit which discharges the internal nodes after current has been delivered to the load, thereby reducing the high voltage stress on the FET gate oxides and improving FET reliability.
These objectives are achieved by connecting diodes, or diode connected transistors, to the internal nodes of the charge pump circuits. The anodes of the diodes are connected to the gates of the FETs in the charge pump circuit The cathodes of the diodes are connected to the output node of the charge pump circuit. When the voltage at the output node of the charge pump circuit is high the diodes have no effect. When current is delivered to the load connected to the output node the voltage at the output node drops and the diodes help discharge the internal nodes of the charge pump circuits thereby reducing the voltage across the FET gate oxides.
REFERENCES:
patent: 5537072 (1996-07-01), Canclini
patent: 5818289 (1998-10-01), Chevallier et al.
patent: 6072358 (2000-06-01), Hung et al.
patent: 6459328 (2002-10-01), Sato
patent: 6674317 (2004-01-01), Chou
patent: 6690227 (2004-02-01), Lee et al.
Callahan Timothy P.
Englund Terry L.
Morris LLP Duane
Taiwan Semiconductor Manufacturing Company
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