Charge pump circuit, PLL circuit, and pulse-width modulation cir

Details Charge pump circuit, PLL circuit, and pulse-width modulation cir Charge pump circuit, PLL circuit, and pulse-width modulation cir

1998-09-25

2000-10-10

Cunningham, Terry D.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327157, G05F 110

Patent

active

061305650

ABSTRACT:
There is described a charge pump circuit capable of minimizing an offset in a phase difference at the time of zero output current, which would otherwise be caused by variations in elements stemming from variations in a manufacturing process. When a first input signal becomes low, a first MOS transistor is brought into conduction, and an electric current "I1" specified by a second MOS transistor flows to an output node as a charge current. When a second input signal becomes low, a third MOS transistor is brought into conduction, and an electric current "I2" specified by a fourth MOS transistor flows to a current mirror circuit. The current mirror circuit withdraws an electric current "I6"--which is the same as that of the electric current "I2"--from the output node as a discharge current. When the charge or discharge current flows to the output node, there is output an electric current of zero. If there is only the charge current, the charge current flows from the output node. In contrast, if there is only the discharge current, the discharge current is withdrawn from the output node.

REFERENCES:
patent: 4697112 (1987-09-01), Ohtani et al.
patent: 4897596 (1990-01-01), Hughes et al.
patent: 5012133 (1991-04-01), Hughes
patent: 5103123 (1992-04-01), McGinn
patent: 5371476 (1994-12-01), Nishioka
patent: 5525927 (1996-06-01), Yung et al.
patent: 5812022 (1998-09-01), Hirano et al.

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