Charge pump circuit for use in a phase locked loop

Details Charge pump circuit for use in a phase locked loop Charge pump circuit for use in a phase locked loop

1997-03-25

1999-03-23

Ton, My-Trang Nu

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327156, H03L 706

Patent

active

058865519

ABSTRACT:
A charge pump circuit in a phase locked loop comprises a main circuit block and an excess current cancel block for canceling a spike current. The spike current is generally supplied by a parasitic capacitance in the main circuit block and generates a jitter in the output of the phase locked loop. The excess current cancel block supplies or drains a cancel current which is substantially equal to the spike current but flows in a reverse direction.

REFERENCES:
patent: 5008637 (1991-04-01), Ray
patent: 5208546 (1993-05-01), Nagaraj et al.
I.A. Young et al.; "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors"; IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1599-1606.
Megmet Soyuer et al: "A Fully Monolithic 1.25GHZ CMOS Frequency Synthesizer", pg. 127, paragraph entitled Circuit Design; figures 1, 3.

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