Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-12-28
2004-01-27
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S534000, C327S535000
Reexamination Certificate
active
06683488
ABSTRACT:
RELATED APPLICATION
The present application claims the benefit of Korean Patent Application No. 87290/2000 filed Dec. 30, 2000, which is herein fully incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a charge pump memory device, and more particularly, to a charge pump device for a semiconductor memory device which produces a step-up voltage for driving wordlines and equalizing bitlines.
2. Background of the Related Art
FIG. 1
is a circuit diagram of a charge pump circuit
10
for a semiconductor device such as a memory device according to a related art. As shown in
FIG. 1
, the charge pump circuit
10
in a semiconductor memory device according to a related art is constructed with three capacitors C
1
to C
3
and six NMOS transistors M
1
to M
6
, operatively coupled. The NMOS transistors M
1
to M
3
are charge transistors for respectively charging nodes N
1
to N
3
to a VDD voltage level, and the capacitor C
1
is a pump capacitor for pumping charges of the node N
1
up to 2VDD. The pump capacitor C
1
is generally larger in size than other capacitors C
2
and C
3
so as to cope properly with the current consumption of the pump circuit
10
.
The NMOS transistors M
5
and M
6
are diode type transistors and supply the nodes N
1
and N
2
with a VDD voltage level. The NMOS transistor M
4
is a transfer transistor for transferring the charges at the node N
1
. The capacitors C
1
to C
3
are connected between input nodes
50
to
52
and the nodes N
1
to N
3
, respectively. The NMOS transistors M
1
to M
3
are connected between the voltage power source VDD and the respective nodes N
1
to N
3
. The gates of the NMOS transistors M
1
and M
3
are connected to the node N
2
in common, while the gates of the NMOS transistors M
2
and M
4
are connected to the node N
3
.
FIGS. 2A-2F
are waveforms for explaining a one-cycle operation of the pump circuit
10
shown in FIG.
1
. As shown in
FIGS. 2A-2F
, an interval A is a pumping interval of the pump capacitor C
1
, and an interval B is a charge interval of the pump capacitor C
1
. During the interval A, the charge at the node N
1
is pumped up to 2VDD which is transferred to an output node
53
through the NMOS transistor M
4
. During the interval B, the node N
1
is charged up to VDD through the NMOS transistor M
1
for the pumping operation of a next cycle.
Just before the beginning of the cycle, when a second clock signal CLK
2
is shifted from VDD to VSS, the potential at the node N
2
is dropped down to VDD from 2VDD due to capacitive coupling (hereinafter “coupling”) provided by the capacitor C
2
. The NMOS transistors M
1
and M
3
are then turned off by the potential VDD of the node N
2
.
Then, at the beginning of the cycle as a first clock signal CLK
1
is shifted up from VSS to VDD, the current potential VDD of the node N
1
having been charged with VDD during the previous cycle rises up to 2VDD due to the pumping operation (coupling) of the pumping capacitor C
1
. Then, as a third clock signal CLK
3
is shifted up from VSS to VDD, the potential of the node N
3
having been charged with VDD by the previous cycle rises up to 2VDD by the coupling of the capacitor C
3
. Then, the potential 2VDD of the node N
3
turns on the NMOS transistors M
2
and M
4
. As a result, the charges 2VDD of the node N
1
having been pumped by the pump capacitor C
1
are transferred to the output node
53
through the NMOS transistor M
4
, and the N
2
is charged with the power source voltage VDD provided through the NMOS transistor M
2
. Consequently, the potential VPP of the output node
53
is increased or pumped by the charges transferred through the NMOS transistor M
4
.
Subsequently, when the third clock signal CLK
3
is shifted down from VDD to VSS in the interval A, the potential of the node N
3
is dropped from 2VDD to VDD by the coupling of the capacitor C
3
, thereby turning off the NMOS transistors M
2
and M
4
. The turned-off NMOS transistor M
4
separates electrically the node N
1
from the output node
53
and the potential VPP of the output node
53
is maintained.
In the interval B, when the first clock signal CLKI is shifted down from VDD to VSS, the node N
1
having the same potential of the output node
53
in the interval A tends to drop down to VNO, min by the coupling of the capacitor C
1
having a very large capacitance. In this case, since the second clock signal CLK
2
is shifted up from VSS to VDD, at the same time the first clock signal CLK
1
is shifted down, the potential of the node N
2
is increased from VDD to 2VDD by the coupling of the capacitor C
2
and the node N
3
is charged with VDD by the NMOS transistor M
3
. The NMOS transistor M
1
is then turned on by the potential 2VDD of the node N
2
, thereby charging the node N
1
with VDD, so that the potential of the node N
1
begins to rise.
However, the potential of the node N
1
experiences an RC delay due to the influence of the resistance (RM
1
) of the NMOS transistor M
1
, the pump capacitor C
1
, and the junction capacitance produced by the NMOS transistors M
1
, M
4
, and MS. Namely, since the charge supplied through the NMOS transistor M
1
is not transferred to the node N
1
fast enough to cope with the abrupt potential drop at the node N
1
as shown in the interval C of
FIG. 2F
, the potential of the node N
1
is dropped down to a level much lower than VDD−Vt
1
wherein Vt
1
is, a threshold voltage of the NMOS transistor M
4
.
On the other hand, the NMOS transistor M
5
is turned on at the moment when the potential of the node N
1
reaches VDD−Vt
2
wherein Vt
2
is a threshold voltage of the NMOS transistor M
5
, thereby charging the node N
1
with VDD. Yet, the charge supplied by the NMOS transistor M
5
is not transferred to the node N
1
fast enough due to the turn-on resistance of the NMOS transistor M
5
and the capacitance of the node N
1
. As a result, the NMOS transistor M
5
, as shown in
FIG. 2F
, starts to operate at the moment when the node N
1
is dropped below VDD−Vt
1
, but is not able to cope quickly with the abrupt potential drop of the node N
1
caused by the coupling of the capacitor C
1
. Thus, during the interval C, the NMOS transistor M
4
is turned on since a voltage difference Vgs between the gate and source voltages of the NMOS transistor M
4
is larger than the threshold voltage Vt
1
of the NMOS transistor M
4
. The charge VPP having been transferred to the output node
53
during the interval A then flows back to the node N
1
through the NMOS transistor M
4
, which decreases the pump efficiency of the pump circuit
10
.
As mentioned in the above explanation, when the operation cycle of the circuit
10
moves from the interval A to the interval B, the pump circuit
10
according to the related art fails to cope quickly with the abrupt potential drop of the node N
1
occurring due to the coupling of the pump capacitor C
1
. This is because charging of the node N
1
with VDD through the NMOS transistor M
1
is delayed by the turn-on resistance of the NMOS transistor M
1
, the capacitance of the pump capacitor C
1
, and the parasitic capacitance of the node N
1
. Consequently, the potential of the node N
1
is dropped to below VDD. This turns on the NMOS transistor M
4
which in turn causes charges from the output node
53
to flow back to the node N
1
. The charges VPP at the output node
53
of the pump circuit
10
is essentially equal to “(supply amount in interval A)-(influx in interval B).” As such, the pump efficiency of the pump circuit
10
according to the related art is decreased by at least the amount of the flow-back charges.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a charge pump circuit and method for a semiconductor memory device with increased pump efficiency that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a charge pump circuit and method for a semiconductor memory device that im
Birch & Stewart Kolasch & Birch, LLP
Hynix / Semiconductor Inc.
Lam Tuan T.
Nguyen Hiep
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