Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2002-07-16
2004-04-27
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S536000, C327S537000, C363S059000, C363S060000
Reexamination Certificate
active
06727735
ABSTRACT:
TECHNICAL FIELD
Phase locked loops are disclosed, and, more particularly, charge pump circuits for reducing jitter in a phase locked loop (PLL) circuit are disclosed.
DESCRIPTION OF THE PRIOR ART
Semiconductor devices, such as a semiconductor memory device and a central processing unit (CPU), generate an internal clock signal using a clock buffer and a clock driver. However, the operating performance of these semiconductor devices deteriorate at high frequencies because the internal clock signal is delayed by a constant time period relative to an external clock signal.
As a result, an output data access time tAC (i.e., the time it takes for the data to be output after inputting the external clock signal), is longer than the generating time of the internal clock signal.
Thus, in order to reduce the performance deterioration of semiconductor devices having a long elapsing output data access time tAC, a circuit for synchronizing the internal clock signal with the external clock signal is required. The circuit for synchronizing the internal clock signal with the external clock signal is called a phase locked loop (PLL) circuit.
FIG. 1
is an internal block diagram of an ordinary prior art phase locked loop (PLL). Referring to
FIG. 1
, a phase locked loop
1000
includes a phase detector
100
, a charge pump circuit
200
, a loop filter
300
, a voltage controlled oscillator (VCO)
400
and a frequency divider
500
. The phase detector
100
compares a standard clock signal, which is in phase with an external clock, with an output phase of the frequency divider
500
. If the output phase of the frequency divider
500
is slower than the phase of the standard clock signal, a pulse (designated as up signal (up)), is outputted from the phase detector
100
in order to increase the frequency. If the output phase of the frequency divider
500
is faster than the phase of the standard clock, a pulse (designated as down signal (down)), is outputted from the phase detector
100
in order to decrease the frequency. The charge pump circuit
200
is responsive to up or down signals received directly from the phase detector, or inverted up and down signals (/up or /down), which is the signal from the phase detector inverted by inverters
110
or
120
.
A pulse output of the charge pump circuit
200
is transmitted to the loop filter
300
. The filter
300
has a resistor
310
and a capacitor
320
. When the down signal is transmitted to the charge pump circuit
200
, an electric charge of the capacitor
320
in the loop filter
300
is reduced. When the up signal (up) is transmitted to the charge pump circuit
200
, the electric charge of the capacitor
320
in the loop filter
300
is increased. The pulse output of the charge pump circuit
200
is transformed into a DC analog signal by the loop filter
200
.
The voltage controlled oscillator
400
receives the DC analog signal from the loop filter
300
and outputs a constant frequency signal. The frequency divider
500
operates as a counter and divides the constant frequency signal from the voltage controlled oscillator
400
into N in order to facilitate comparison at the phase detector
100
.
In the phase locked loop
1000
, the phase detector
100
, the charge pump circuit
200
, the voltage controlled oscillator
400
and the frequency divider
500
are formed as a loop to control the phase. The number of the output frequency is N-fold increase relative to the number of the input frequency. N is set to a temporary value to get a natural multiple frequency of the input frequency.
FIG. 2A
is an internal circuit diagram of a prior art charge pump circuit
200
used in FIG.
1
. Referring to
FIG. 2A
, the internal circuit of the charge pump circuit
200
includes a first transistor MP
1
. An operating voltage VDD is provided through a drain of the first transistor and a bias voltage Vbiasp is applied through a gate of the first transistor for maintaining the turn-on state. The circuit
200
includes a second transistor MP
2
. A source of the first transistor MP
1
is connected to a drain of the second transistor, and the up signal (up) is input to a gate of the second transistor. A third transistor MN
2
, is connected to the source of the second transistor MP
2
. The down signal is input to a gate of the third transistor MN
2
. A fourth transistor MN
1
is connected to a source of the third transistor MN
2
. A bias voltage Vbiasn is applied to a gate of the fourth transistor MN
1
for maintaining the turn-on state.
The first and second transistors MP
1
and MP
2
are P channel MOS transistors and the third and fourth transistors MN
2
and MN
1
are N channel MOS transistors. Furthermore, an output terminal OUT is connected commonly with the source of the second transistor MP
2
and the drain of the third transistor MN
2
.
FIG. 2B
is an equivalent circuit when the charge operation of the charge pump is performed by the up signal (up).
FIG. 2C
is an equivalent circuit when the discharge operation of the charge pump is performed by the down signal.
Referring to
FIG. 2B
, when the low level inverted up signal (/up) is input to the second transistor MP
2
, the second transistor is turned on and the operating voltage VDD applied to the drain of the first transistor MP
1
is charged through the output terminal OUT because the transistor MP
1
is in the turn on state.
Referring to
FIG. 2C
, when the high level down signal is input to the third transistor MN
2
, the third transistor is turned on and a charged voltage is discharged through a ground VSS because the fourth transistor MN
1
is in the turn on state, and the output terminal OUT and the ground VSS are shorted.
As shown in
FIG. 2B
, a parasitic capacitance Cfp is generated between the operating voltage VDD and a node C. Thus, when the first transistor MP
1
is changed from the turn off state to the turn on state, the potential of the node C is changed from a power potential to the output terminal OUT potential and a current Icfp flows based on such potential difference and parasitic capacitance Cfp.
Furthermore, a parasitic capacitance Cfn is generated between the ground and a node D. (See FIG.
2
C). Thus, when the third transistor MN
2
is changed from the turn off state to the turn on state, the node D is changed from the ground potential to the output terminal OUT potential and a current Icfn based on such potential difference and parasitic capacitance Cfn.
Therefore, a charge sharing occurs because of the parasitic capacitance so that the current supply from the output terminal OUT is unstable.
That is, overshoots occur in the output current of the charge pump circuit because of the current icfp or icfn. Thus, a jitter occurs in the voltage controlled oscillator
400
, which is connected to the output terminal OUT. As a result, an error is generated in the system because the system is controlled repeatedly by the output signal of the voltage controlled oscillator
400
.
This problem can be eliminated by forming the potential of nodes C and D when transistors MP
2
and MN
2
are in the turn off state. However, the potential of nodes C and D are identical to the potential of the output terminal OUT.
FIG. 3
is a prior art charge pump circuit
200
′ for controlling the charge sharing when the up or down signal (up or down) are switched. Referring to
FIG. 3
, the charge pump circuit
200
′ includes a first transistor MP
1
(wherein an operating voltage VDD is provided through a drain and a bias voltage Vbiasp is applied through a gate for maintaining the turn-on state), a second transistor MP
2
(wherein a source of the first transistor MP
1
is connected and the inverted signal (/up) is input through a gate), a third transistor MP
3
(wherein a source of the second transistor MP
2
is connected and the up signal (up) is input through a gate), a fourth transistor MN
2
(wherein a source of the second transistor MP
2
is connected and the down signal is inputted through a gate), a fifth transistor MN
3
(wherein a source of the third transistor MP
3
is connected and
Callahan Timothy P.
Hynix / Semiconductor Inc.
Luu An T.
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