Static information storage and retrieval – Floating gate – Particular connection
Patent
1994-10-19
1996-01-09
Popek, Joseph A.
Static information storage and retrieval
Floating gate
Particular connection
36518909, 365226, 327536, G11C 1134
Patent
active
054834864
ABSTRACT:
A circuit for generating one of a plurality of output voltages. The circuit includes a first conductor coupled to a first supply voltage, a second conductor coupled to a second supply voltage, a charge pump having an input and an output, a multiplexor, a first regulation circuit, and a second regulation circuit. The first regulation circuit is coupled to the first input of the multiplexor and the output of the charge pump. The first regulation circuit is for generating a first regulation voltage in response to the first supply voltage and the output of the charge pump such that the charge pump outputs a first output voltage when the first input of the multiplexor is coupled to the output of the multiplexor. The second regulation circuit is coupled to the second input of the multiplexor and the output of the charge pump. The second regulation circuit is for generating a second regulation voltage in response to the second supply voltage and the output of the charge pump such that the charge pump outputs a second output voltage when the second input of the multiplexor is coupled to the output of the multiplexor. The multiplexing of the regulation circuitry results in a reduced number of components.
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1992 IEEE International Solid-State Circuits Conference, ISSCC 92 Session 9/Non-Volatile and Dynamic Rams/Paper 9.3, "TP9.3: A 5V-Only 0.6 .mu.m Flash EEPROM with Row Decoder Scheme in Triple-Well Structure", Masao Kuriyama, Shigeru Atsumi, Akira Umezawa, Hironori Banba, Ken-ichi Imamiya, Kiyomi Naruke, Seiji Yamada, Etsuishi Obi, Masamitsu Oshikiri, Tomoko Suzuki, Sumio Tanaka, pp. 152-153.
Javanifard Jahanshir J.
Landgraf Marc E.
Intel Corporation
Popek Joseph A.
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