Charge pump circuit for a semiconductor memory device

Details Charge pump circuit for a semiconductor memory device Charge pump circuit for a semiconductor memory device

1998-11-19

2001-01-23

Mai, Son (Department: 2818)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S589000, C365S189090

Reexamination Certificate

active

06177828

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device, and more particularly, to an improved charge pump circuit for a semiconductor memory device.
2. Background of the Related Art
FIG. 1
illustrates a charge pump circuit for a related art semiconductor memory device. An oscillator
11
receives an enable signal, carries out an oscillation operation, and generates a pulse signal. First and second clamps
12
,
14
fix the pulse signal generated from the oscillator
11
to a constant potential level when the potential of the pulse signal generated from the oscillator
11
is higher than a predetermined value. The capacitors
13
,
15
are connected in parallel between the oscillator
11
and the first clamp
12
and the second clamp
14
and boosts the potential of the pulse signal outputted from the oscillator
11
to a required voltage level. An output transistor
16
has a drain connected to an output signal of the capacitor
13
, a gate connected to an output signal of the capacitor
15
, and a source connected to an output node
17
.
Pull-up transistor
18
is connected between the output node
17
and a supply potential Vcc and carries out a precharge operation when power is turned on. An overvoltage detector
19
is connected between the oscillator
11
and the output node
17
and detects an overvoltage state of the output node
17
so that when an overvoltage occurs at the output node
17
, the oscillator
11
stops its operation. The line capacitor
20
and the charge capacitor
21
are cooperated with an output value of the output capacitor
16
so as to output a raised voltage. The decoupling capacitor
22
is cooperated with a charge pump so as to output a stably raised voltage.
When the power is turned on, a supply potential Vcc is applied to the pull-up transistor
18
. The applied supply potential Vcc is lowered by a threshold voltage level Vt of the pull-up transistor
18
, and a lowered voltage of (Vcc−Vt) is applied to the output node
17
. The voltage (Vcc−Vt) precharged to the output node
17
is detected in the overvoltage detector
19
.
Since the voltage (Vcc−Vt) detected in the overvoltage detector
19
is lower than the supply voltage Vcc, the overvoltage detector
19
outputs an enable signal EN to the oscillator
11
for thereby operating the oscillator
11
. Accordingly, the oscillator
11
carries out an oscillation operation and generates a pulse signal.
When the potential generated from the oscillator
11
is a low level, the first and second clamps
12
,
14
are deactivated, and the capacitors
13
,
15
carry out a pumping operation. Accordingly, the respective potentials at the drain and gate of the output transistor
16
is raised to twice the supply potential Vcc. The output transistor
16
is turned on, and a source terminal voltage Vccw of the output transistor
16
reaches a voltage of (2Vcc−Vt), where Vt is a threshold voltage of the output transistor
16
. The voltage of (2Vcc−Vt) is applied to a memory cell through the output node
17
.
At this time, the overvoltage detector
19
repeatedly detects the voltage at the output node
17
and controls the operation of the oscillator
11
in accordance with the detected voltage value. The repeated detection by the overvoltage detector
19
continues until a detected resultant value reaches up to a potential (Vcc+Vt). When an overvoltage is detected during the repeated operation, the overvoltage detector
19
renders the oscillator
11
to stop its operation.
Meanwhile, when the voltage supplied to the charge pump is not appropriate, the pull-up transistor
18
is employed to effectively bypass the charge pump. That is, the pull-up transistor
18
is operated when the source terminal voltage Vccw is less than a voltage of Vcc−Vt (Vccw<(Vcc−Vt)), and the pull-up transistor
18
is turned off when the source terminal voltage Vccw is larger than a voltage of Vcc−Vt (Vccw>(Vcc−Vt)).
However, the potential of the drain and gate terminals of the output transistor
16
during a pumping operation is twice the supply voltage (2Vcc), whereas the voltage at the output node
17
is lowered to an extent of the threshold voltage of the output voltage
16
to thereby result in a voltage of (2Vcc−Vt). As a result, the charge at the drain terminal of the output transistor
16
is not sufficiently transferred to the output node
17
. Further, because the drain terminal charge of the output transistor
16
is not sufficiently transferred to the output node
17
, the pumping efficiency is lowered at a low voltage, thereby resulting in an instable operation when a low voltage is applied.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a charge pump circuit having a high efficiency for a semiconductor memory device capable of generating a raised voltage using a supply voltage provided from an exterior of the chip or an internal voltage, and outputting the generated high voltage to an output node without loss.
It is another object of the present invention to provide a charge pump circuit having a high efficiency for a semiconductor memory device which makes it possible to immediately supply charge to an output node having a low voltage level and carry out a stable operation by enhancing a pumping efficiency.
It is a further object of the present invention to provide a charge pump circuit having a high efficiency for a semiconductor memory device capable of decreasing electrical power amount by supplying an appropriate amount of charge to an output node having a high voltage.
To achieve the above-described objects, there is provided a charge pump circuit having a high efficiency for a semiconductor memory device which includes a high voltage detector for outputting a high voltage detection signal when an applied supply voltage reaches up to a predetermined voltage level, a regulator for outputting a high level on signal when a raised voltage is lowered below a predetermined voltage while detecting the raised voltage being applied during a power-on, a controller for being triggered at a descent edge of a row access strobe bar signal and outputting a high level row access strobe bar pulse signal, an oscillator for generating an oscillation pulse signal in accordance with the high level turn-on signal outputted from the regulator, a charge pump for carrying out a pumping operation until the oscillation pulse signal reaches up to a potential value (Vdd+2Vt) when the oscillation pulse signal is applied thereto from the oscillator, and halting the pumping operation when the high level high-voltage detection signal is applied, a pull-up transistor for precharging the raised voltage Vpp to a potential value (Vdd−Vt) when power is turned on, and a decoupling capacitor connected to a final output terminal and for carrying out a charge accumulation and a decoupling operation.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.


REFERENCES:
patent: 5982222 (1999-11-01), Kyung
patent: 6023187 (2000-02-01), Camacho et al.
patent: 0 206 785 (1986-12-01), None
patent: 0 449 235 A2 (1991-10-01), None
patent: 0 596 228 A1 (1994-05-01), None
patent: 2 244 392 (1991-11-01), None

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