Charge pump circuit for a PLL

Details Charge pump circuit for a PLL Charge pump circuit for a PLL

2005-10-04

2005-10-04

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

Reexamination Certificate

active

06952126

ABSTRACT:
A technique is disclosed for providing a charge pump circuit for phase locked loop (PLL) to reduce mismatch of up/down currents and feed-through of up/down currents to voltage output. Elimination of feed-through of the input signal may be achieved by using differential switches (M1and M2, and M3and M4) based on DC reference voltage in the charge pump and also eliminate the mismatch of up/down currents in a wide voltage output range by applying a new replica biasing using feedback.

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patent: 000052532 (2000-08-01), None
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Samavati, Hirad, et al., A Fully-Integrated 5 GHz CMOS Wireless-LAN Receiver, Stanford University, Stanford, CA, 2001 IEEE International Solid State Circuits Conference, 2001.

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