Charge pump circuit for a high speed phase locked loop

Details Charge pump circuit for a high speed phase locked loop Charge pump circuit for a high speed phase locked loop

2001-11-06

2003-08-26

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S148000

Reexamination Certificate

active

06611161

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuit technology. The present invention provides an improved charge pump circuit that suppresses charge sharing due to static phase error in a high speed phase locked loop circuit.
BACKGROUND OF THE INVENTION
Phase locked loop circuits are well known.
FIG. 1
illustrates a block diagram of a prior art frequency synthesizer charge pump phase locked loop (PLL) circuit
100
. Input signal FIN is provided to input divider
110
and an external clock signal RFC from input provider
110
is provided to a first input of phase frequency detector
120
. Phase frequency detector
120
provides an “up” signal (designated “UP”) and a “down” signal (designated “DN”) to charge pump
130
. As is well known in the art, the UP signal closes a switch to cause current source
140
to provide current I
UP
to the output line of charge pump
130
. The DN signal closes a switch to cause current source
150
to draw current I
DN
from the output line of charge pump
130
.
The output line of charge pump
130
is coupled to loop filter
160
and to voltage controlled oscillator (VCO)
170
. The currents from charge pump
130
adjust the phase of the voltage controlled oscillator
170
. The output signal F
OUT
from voltage controlled oscillator
170
is provided to feedback divider
180
. An internal clock feedback signal FBC from feedback divider
180
is provided to a second input of phase frequency detector
120
. Phase frequency detector
120
compares the FBC signal from feedback divider
180
with the RFC signal from input divider
110
.
A charge pump PLL is a negative feedback system that insures that the phase difference as well as the frequency difference at the input of phase frequency detector
120
is near zero under steady state conditions. A PLL in such a state is said to be in a “lock” condition or “locked.” The input and output frequencies are related by a fixed ratio which can be selected by choosing the values of the input divider
110
and the feedback frequency divider
180
.
A charge pump PLL is typically a second order system. Therefore, any change from the steady state condition will result in a transient response that is typically characterized by the damping factor and the natural frequency of the system. The damping factor and the natural frequency of the system are dependent upon physical quantities such as the charge pump current, the effective gain of the voltage controlled oscillator
170
, the parameters of loop filter
160
, and properties of the phase frequency detector
120
. The settling behavior of the transient response may also be governed by the comparison frequency at the input of the phase frequency detector
120
.
The output of phase frequency detector
120
comprises pulses at the UP output pin and at the DN output pin such that the difference in the pulse widths of the UP signal and the DN signal is equal to the input phase difference. The UP and DN signals are provided to charge pump
130
. In response, charge pump
130
dumps an equivalent charge to adjust the phase of the voltage controlled oscillator
170
. In a locked state, the output of phase frequency detector
120
comprises narrow pulses of equal duration on the UP output pin and on the DN output pin. The use of narrow pulses even in the locked state prevents the formation of a dead zone for small phase differences at the input of phase frequency detector
120
.
There are deviations from ideal behavior in a practical system. For example, the “up” current I
UP
and the “down” current I
DN
in charge pump
130
are not exactly equal due to the finite output impedance of current source
140
and current source
150
. There can also be delay mismatches between the UP signal and the DN signal at the output of phase frequency detector
120
. Leakage in loop filter
160
may also affect the operation of the charge pump PLL system.
Because the charge pump PLL system is a negative feedback system, the PLL corrects for all the non-ideal conditions by having a small phase offset at the input of the phase frequency detector
120
of an appropriate magnitude and polarity to negate these effects. This phase difference at the input of the phase frequency detector
120
is called the “static phase error.”
FIG. 2
illustrates a circuit diagram of a charge pump circuit
130
comprising a prior art charge sharing suppression circuit
200
capable of suppressing charge sharing due to parasitic capacitances within charge pump circuit
130
.
Switch S
1
in charge pump circuit
130
closes when switch S
1
receives an up signal. Switch S
2
in charge pump circuit
130
closes when switch S
2
receives a DN signal. Output line
210
of charge pump circuit
130
outputs a control voltage V
CONTROL
to loop filter
160
and to voltage controlled oscillator
170
.
Charge sharing suppression circuit
200
comprises signal line
220
and signal line
230
. A first end of signal line
220
is coupled to the output of current source
140
at node N
1
. A first end of signal line
230
is coupled to the input of current source
150
at node N
2
. A second end of signal line
220
and a second end of signal line
230
are coupled together at node N
3
.
A first input of amplifier
240
is coupled to output line
210
. The output of amplifier
240
is coupled to node N
3
. The output of amplifier
240
is also coupled to a second input of amplifier
240
to place amplifier
240
in a unity gain configuration.
Switch S
3
is located within signal line
220
. Switch S
3
closes when switch S
3
receives an inverted UP signal (denoted as UPB). Switch S
4
is located within signal line
230
. Switch S
4
closes when switch S
4
receives an inverted DN signal (denoted as DNB).
The current I
UP
from current source
140
and the current I
DN
from current source
150
need to be equal. Therefore, when node N
1
and node N
2
are not switched to V
CONTROL
(i.e., when switch S
1
and switch S
2
are open) then node N
1
and node N
2
are biased by unity gain amplifier
240
because switch S
3
and switch S
4
are closed. This suppresses the charge sharing from parasitic capacitance on node N
1
or node N
2
that can cause mismatch between current source
140
and current source
150
.
Prior art charge sharing suppression circuit
200
operates correctly when the PLL is locked and there is no static phase error. However, if there is any static phase error due to the difference in arrival times of the UP signal and the DN signal there will be no return path for the charge pump currents during the duration of the static phase error.
For example, consider the UP signal and the DN signal shown in FIG.
3
. The DN signal arrives before the UP signal arrives. During the time of the static phase error there is a mismatch in the signals in that the DN signal is present but the UP signal is not. There is no return path for the current I
UP
because switch S
3
is closed (by the signal UPB) while switch S
4
is still open (by the absence of the signal DNB). This condition will cause node N
1
to charge up to the voltage V
dd
. The extra charge is redistributed on the loop filter
160
during the next comparison cycle. This leads to low frequency jitter.
A similar situation occurs when an UP signal arrives before a DN signal. During the time of the static phase error there is a mismatch in the signals in that the UP signal is present but the DN signal is not. There is no return path for the current I
DN
because switch S
4
is closed (by the signal DNB) while switch S
3
is still open (by the absence of the signal UPB). This condition will cause node N
2
to charge down to the voltage V
ss
. The extra charge is redistributed on the loop filter
160
during the next comparison cycle. This also leads to low frequency jitter.
It would be desirable to have a charge pump circuit in a phase locked loop circuit that is capable of suppressing charge sharing due to static phase error within the charge pump circuit.
It would also be desirable to have a charge pump circ

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