Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-09-13
2002-06-18
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S538000, C327S541000, C327S147000, C323S313000, C323S315000, C363S059000, C363S060000
Reexamination Certificate
active
06407619
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a charge pump circuit and a phase-locked loop (hereinafter referred to as “PLL”) circuit using the charge pump circuit, and in particular to measures against a dead band in the charge pump circuit, and to improvements in the C/N (Carrier/Noise) ratio in the PLL circuit which are required in connection with this measures.
This application is based on Japanese Patent Application No. Hei 11-259950, the contents of which are incorporated herein by reference.
2. Description of the Related Art
A PLL frequency synthesizer (hereinafter referred to as “PLL circuit”) is an oscillator which outputs, based on a single reference frequency signal, an output signal having an arbitrary frequency in accordance with a frequency dividing ratio of a frequency divider, which is set to a desired value supplied from the outside of the PLL circuit, and PLL circuits are applied to various circuits. For a PLL circuit to function as an oscillator, it must have a superior C/N ratio, i.e., the ratio of the oscillation frequency signal (Carrier) to the noise.
FIG. 7
is a block diagram showing the structure of a general PLL circuit. This PLL circuit comprises a phase comparator
2
, a charge pump circuit
3
, a low pass filter (LPF)
4
, a voltage controlled oscillator (VCO)
5
, and an N-frequency divider
6
. The phase comparator
2
receives the signal having a reference frequency f
r
from a reference oscillator
1
, and compares the reference frequency f
r
with a divided frequency f
s
, so as to calculate the phase difference between these frequencies. The charge pump circuit
3
outputs a charge pump current I
out
based on the comparison result output from the phase comparator
2
. The LPF
4
eliminates the components of an alternating current from the charge pump current I
out
. The VCO
5
outputs the oscillation signal having an output frequency f
out
based on the direct current voltage which is input from the LPF
4
. The N-frequency divider
6
divides the frequency of the signal having the output frequency f
out
into 1/N, and outputs the divided signal having a divided frequency f
s
. In addition, in the phase comparator
2
, a signal having the reference frequency f
r
is supplied to a reference input terminal, and a signal having the divided frequency f
s
is supplied to a comparison input terminal. Thus, the PLL circuit outputs the signal having the output frequency f
out
as the output of the VCO
5
, which is subjected to feedback control, in accordance with a frequency dividing ratio N for the N-frequency divider
6
supplied from the outside of the PLL circuit.
The phase comparator
2
outputs two signals as comparison result signals. In other words, the phase comparator
2
calculates the phase difference for the divided frequency f
s
with respect to the reference frequency f
r
as a standard, and if the phase difference indicates a lagging phase, the comparator makes a phase comparison signal Eup valid, while if the phase difference indicates a leading phase, the comparator makes a phase comparison signal Edown valid. The charge pump circuit
3
functions as a booster or a voltage dropper, and, based on the two comparison signals, supplies charge to the input of the LPF
4
or extracts charge from the input of the LPF
4
. Some proposals have been made for techniques using such charge pump circuits, and one of these is disclosed, for example, in Japanese Unexamined Patent Application, First Publication, No. Hei 10-13221. In addition, charge pump circuits for PLL circuits where measures against a dead band are taken have also been proposed.
FIG. 3
is a circuit diagram showing the structure of a conventional charge pump circuit corresponding to a PLL circuit where measures against a dead band are taken. For example, in the PLL circuit shown in
FIG. 7
, when the phases of two signals which are input into the phase comparator
2
are the same, a period in which both phase comparison signals Eup and Edown are set to high (hereinafter referred to as “dead band prevention period”) is provided as a measure against dead bands. A charge pump circuit
3
A shown in
FIG. 3
comprises first and second current mirror circuits. The first current mirror circuit comprises a first reference current path
25
which sets a node NA to a first reference potential in response to the phase comparison signal Eup, and a first output current path
23
which passes a charge-up current Iup in response to the first reference potential. On the other hand, the second current mirror circuit comprises a second reference current path
26
which sets a node NB to a third reference potential in response to the phase comparison signal Edown, and a second output current path
24
which passes a charge-down current Idown in response to the third reference potential.
When the phase comparison signal Eup is low, the first reference current path
25
sets the node NA to a predetermined high potential, so that the source-drain path in a p-type transistor M
2
falls into a complete cutoff state, and the charge-up current Iup is set to zero. Moreover, when the phase comparison signal Eup is high, the first reference current path
25
sets the node NA to the first reference potential, so that the state of the source-drain path in the p-type transistor M
2
changes from the complete cutoff state to a state in which a drain current of 6 mA flows. Consequently, the charge-up current Iup is set to 6 mA.
Next, the second reference current path
26
sets the node NB to a predetermined low potential when the phase comparison signal Edown is low, so that the source-drain path in an n-type transistor M
5
falls into a complete cutoff state, and the charge down current Idown is set to zero. Moreover, the second reference current path
26
sets a node NB to the third reference potential when the phase comparison signal Edown is high, the state of the source-drain path in the n-type transistor M
5
changes from a complete cutoff state to a state in which a drain current of 6 mA flows. Consequently, the charge down current Idown is set to 6 mA.
FIGS. 4A
to
4
C are timing charts showing the timing in the charge pump circuit shown in
FIG. 3
where the results obtained by the simulation using the SPICE (Simulation Program with Integrated Circuit Emphasis) are shown. When the phase difference between the reference frequency signal f
r
and the divided frequency signal f
s
is approximately zero (hereinafter referred to as “in-phase timing”), the phase comparator
2
increases the levels of the phase comparison signals Eup and Edown to high.
FIG. 4A
is a timing chart showing the timing of the phase comparison signals Eup and Edown in which periods of time of 10 ns to 30 ns are set as dead band prevention periods. Moreover,
FIG. 4B
is a timing chart showing the timing of the charge-down current Idown and the charge-up current Iup. Furthermore,
FIG. 4C
is a timing chart showing the timing of the charge pump current I
out
which is the difference between the charge-up current Iup and the charge-down current Idown.
The rise time of the charge pump current in which each of the charge-up current Iup and the charge-down current Idown increases from 0 mA to 6 mA is 20.9 nanoseconds, and the switching of the current results in a noise current whose duration is equal to or below one nanosecond immediately after the change in the charge pump current I
out
. In addition, it is necessary to extend the dead band prevention period in accordance with the increase in the rise time of the charge pump current I
out
.
In the conventional technology as stated above, the period for the measures to prevent dead bands have to be long, so that the increase in noise accompanied by such a dead band prevention period causes the problem of a deterioration of the C/N ratio of the PLL circuit.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a charge pump circuit which can obtain a short rise time of a charge pump current. Another object o
Luu An T.
Wells Kenneth B.
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