Charge pump circuit and PLL circuit using same

Details Charge pump circuit and PLL circuit using same Charge pump circuit and PLL circuit using same

2005-07-19

2005-07-19

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S536000, C327S537000, C363S059000, C363S060000

Reexamination Certificate

active

06919746

ABSTRACT:
A charge pump circuit able to enhance the rising and falling characteristics of a current output, drive the current output with a short pulse, reduce leakage current at the OFF time when a current is not output, and realize a reduction of a power consumption and a PLL circuit using same. By outputting a charge current or a discharge current in accordance with an up signal or a down signal and turning on a third transistor (PC, NC) at the OFF time when the current is not output, an inverse bias voltage is supplied between a gate and a source of the second transistor (PA, NA), whereby a reduction of the leakage current can be realized. When the second or third transistor is switched in accordance with the up signal or the down signal, the timing of the control signal is appropriately controlled, simultaneous turning on of the second and third transistors can be avoided, release or injection of charges from and to the output terminal of the charge pump circuit can be prevented, and the stability of an oscillation frequency of a VCO can be improved.

REFERENCES:
patent: 5825640 (1998-10-01), Quigley et al.
patent: 6441660 (2002-08-01), Ingino, Jr.
patent: 6456513 (2002-09-01), Saito
patent: 1 037 366 (2000-09-01), None
patent: 2000-269808 (2000-09-01), None
patent: 2001 177400 (2001-06-01), None
A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocesors, IEEE Journal of Solid-State Circuits, vol. 127, No. 11, Nov. 1992, pp. 1599-1607.
EPO Search Report Mar. 29, 2004.

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