Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-05-30
2002-08-20
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S534000, C327S157000
Reexamination Certificate
active
06437637
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a charge-pump circuit outputting voltage fluctuation within a step of power source voltage Vdd and a control method thereof, particularly a control method of a charge-pump circuit capable of normal charging pump operation removing influence of a parasitic diode following to a charge transfer device.
The charge-pump circuit developed by Dicson generates higher voltage than power source voltage Vdd of an LSI chip by voltage fluctuation of each pumping packet connecting plural stages of the pumping packet in series. For example, it is used for generating voltage for program/erase of flash memories.
However, the conventional charge-pump circuit carries out voltage fluctuation with a step of the power source voltage Vdd, and a circuit capable of carrying out voltage fluctuation with lower voltage step than the Vdd was not yet proposed. So, the inventor has already proposed a charge-pump circuit capable of carrying out voltage fluctuation with lower voltage step than the Vdd and improving efficiency &eegr; of the circuit (U.S. patent application Ser. No. 09/732,944 filed on Dec. 8, 2000).
The outline thereof will be described below. FIG.
17
and
FIG. 18
are circuit diagrams showing a structure and an operation of −0.5 Vdd voltage fluctuation charge-pump circuit. The charge-pump circuit generates voltage of voltage fluctuation of −0.5 Vdd to earth voltage (0 V).
In
FIG. 17
, diodes D
1
and D
2
are connected in series as charge transfer devices. To a cathode of the diode D
1
, earth voltage (0 V) is supplied. The diodes D
1
and D
2
generally consist of MOS transistors for charge transfer in order to integrate into an LSI.
Switches S
1
, S
2
and S
3
connect two capacitors
1
and
2
to a connecting point between the diodes D
1
and D
2
switching in parallel or in series. These switches S
1
, S
2
and S
3
can consist of MOS transistors. Thus, on and off of the switches S
1
, S
2
and S
3
corresponds to on and off of the MOS transistors. A clock driver
3
supplies clock CLK to the capacitor
2
. Output voltage output from the diode
2
is applied to a load
4
.
An outline of control method of the charge-pump circuit will be described below. Power source voltage of Vdd the clock driver is assumed 5 V. Although forming the diodes D
1
and D
2
and the switches S
1
, S
2
and S
3
actually occurs voltage drop, the voltage drop is assumed 0 V omitting the voltage drop here.
When input clock of the clock driver
3
is high level (CLK=High), assuming that S
1
is off, S
2
is on and S
3
is off, two capacitors
1
and
2
are connected in series and each node voltage is: VL
1
≈0V, VA=VB=2.5V, VC=5V.
VL
1
is voltage of a connecting node between the diode D
1
and the capacitor
1
(a pumping node), VA is voltage of a connecting node between the capacitor C
1
and the switch S
2
, VB is voltage of a connecting node between the switch S
2
and the capacitor
2
, and VC is voltage of a connecting node between output of the clock driver
3
and the capacitor
2
.
That is, if capacitance values which capacitors
1
and
2
have are equal, capacitors
1
and
2
are respectively charged to voltage of Vdd/2 by distributing equally electric charge to the capacitors
1
and
2
(see FIG.
17
).
Next, when the input clock CLK is transferred to low level (CLK=Low) from the state of the parallel connection, each node voltage becomes: VL
1
≈2.5V, VA=0V, VB=−2.5V, VC=5V by effect of the capacitor coupling because the capacitors
1
and
2
are connected to the pumping node (See FIG.
18
).
Thus, by repeating switching the capacitors
1
and
2
alternately to series and parallel according to the input clock CLK, output voltage of −2.5 V (=(−1/2)·Vdd) is supplied to the load
4
from the diode D
2
.
In order to integrate the charge-up pump of the above-mentioned structure, the switches S
1
, S
2
and S
3
consist of MOS transistors for control M
1
, M
2
and M
3
as shown in FIG.
19
and FIG.
20
. To a gate of the MOS transistor for control M
2
, control clock {overscore (CLKs)} is applied. To a gate of the MOS transistor for control M
3
, control clock {overscore (CLKp)} is applied. When the control clock {overscore (CLKs)} is low level, the MOS transistor for control M
2
turns on and the capacitors
1
and
2
are connected in series.
When the control clock {overscore (CLKp)} is low level, the MOS transistors for control M
1
and M
3
turn on and the capacitors
1
and
2
are connected in parallel. Here, it is assumed that substrates of the MOS transistors for control M
1
and M
2
are biased by voltage of the node B in the figure, It is assumed that a substrate of the MOS transistor for control M
3
is biased by output of the clock driver
3
.
As shown in
FIG. 19
, when the input clock CLK from the clock driver
3
is high level (CLK=High), the control clock {overscore (CLKs)} is low level and the control clock {overscore (CLKp)} is high level, the MOS transistors for control M
1
and M
2
turn off and the MOS transistors for control M
2
turns on. That is, the capacitors
1
and
2
are connected in series. At this time, aiming at a parasitic PN junction diode Dp accompanying the MOS transistor for control M
2
, there is not any problem because the parasitic PN diode Dp is not biased to forward direction.
The parasitic PN junction diode Dp is formed between a P-type drain (node A in the figure) and an N-type substrate of the MOS transistor for control M
2
.
However, as shown in
FIG. 20
, when the input clock CLK is low level (CLK=Low), the control clock {overscore (CLKs)} is high level and the control clock {overscore (CLKp)} is low level, the MOS transistors for control M
1
and M
3
turn on and the MOS transistors for control M
2
turns off. That is, the capacitors
1
and
2
are connected in parallel. At this time, aiming at a parasitic PN junction diode Dp accompanying the MOS transistor for control M
2
, there is a problem that the parasitic PN diode Dp is biased to forward direction.
Drain voltage of the MOS transistor for control M
2
is: Vdrain=VA=0V. Source voltage of the MOS transistor for control M
2
is: Vsource=VB=−2.5 V. That is, drain potential is higher 2.5 V than substrate potential. Then, a parasitic PN junction diode Dp
1
consisting of the drain and the substrate of the MOS transistor for control M
2
is biased to forward direction.
That is, the following relation holds: drain voltage Vdrain −substrate voltage Vbody>VF. Here, VF is forward direction threshold voltage of the diode. Thus, needless forward direction current of the diode flows and there has been problems of incorrect movement of the charge-pump circuit and increase of current consumption.
SUMMARY OF THE INVENTION
An object of the invention is to prevent that forward direction current flows substantially through the parasitic PN junction diode accompanying the MOS transistor for control connecting the capacitors in series, to make normal operation of the charge-pump circuit possible and to prevent increase of current consumption at operation of voltage fluctuation of the charge-pump circuit in the charge-pump circuit carrying out voltage fluctuation of lower voltage step than Vdd.
A charge-pump circuit of the invention comprises, at least first and second electrical charge transfer devices connected in series, first and second capacitors, clock supplying means supplying clock to one end of the second capacitor, first switching means for connecting said first and second capacitors to a connecting point of the first and second electrical charge transfer devices in series, and second switching means for connecting said first and second capacitors to the connecting point of the first and second MOS transistors for electrical charge transfer in parallel, wherein at least said first switching means consists of a MOS transistor for control and the charge-pump circuit has means for biasing a sub
Fish & Richardson P.C.
Lam Tuan T.
Nguyen Hiep
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