Charge pump circuit allowing efficient electric charge transfer

Details Charge pump circuit allowing efficient electric charge transfer Charge pump circuit allowing efficient electric charge transfer

1999-12-15

2002-11-12

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C365S189200

Reexamination Certificate

active

06480057

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a charge pump circuit, and more particularly to a charge pump circuit transferring positive electric charge or negative electric charge of an input node to an output node in synchronization with a clock signal.
2. Description of the Background Art
Conventionally, a flash memory includes a positive charge pump circuit and a negative charge pump circuit to generate a high voltage for data writing and data erasing (see FIG.
1
).
FIGS. 19A
to
19
C are circuit block diagrams showing a structure of a conventional positive charge pump circuit.
In
FIG. 19A
, the positive charge pump circuit includes an N channel MOS transistor
101
and N (where N is an even number) stage charge pump unit circuits
102
.
1
-
102
.N connected in series. N channel MOS transistor
101
is diode connected between a line of power supply potential VCC and an input node of charge pump unit circuit
102
.
1
of the first stage.
Charge pump unit circuits
102
.
1
,
102
.
3
, . . . ,
102
.N−1 located at odd-numbered stages supply positive charge to charge pump unit circuits
102
.
2
,
102
.
4
, . . . ,
102
.N located next to them, respectively, in synchronization with clock signals CLK
11
and CLK
12
. Charge pump unit circuits
102
.
2
,
102
.
4
, . . . ,
102
.N located at even-numbered stages supply positive charge to charge pump unit circuits
102
.
3
,
102
.
5
, . . . ,
102
.N−1 located next to them and to an output node, respectively, in synchronization with clock signals CLK
13
and CLK
14
. An output potential of charge pump unit circuit
102
.N of the last stage is an output potential VO of the positive charge pump circuit.
Charge pump unit circuit
102
.
1
includes an N channel MOS transistor
103
, a resistance element
104
, and capacitors
105
and
106
as shown in
FIG. 19B. N
channel MOS transistor
103
is connected between an input node N
102
and an output node N
103
of charge pump unit circuit
102
.
1
. Resistance element
104
is connected between a gate of N channel MOS transistor
103
and an input node N
102
. Capacitor
105
has one electrode receiving clock signal CLK
11
and another electrode connected to input node N
102
. Capacitor
106
has one electrode receiving clock signal CLK
12
and another electrode connected to the gate of N channel MOS transistor
103
.
Charge pump unit circuits
102
.
3
,
102
.
5
, . . . ,
102
.N−1 of odd-numbered stages are each of the same structure with charge pump unit circuit
102
.
1
. Charge pump unit circuit
102
.
2
,
102
.
4
, . . . ,
102
.N of even-numbered stages are each same with charge pump unit circuit
102
.
1
except that clock signals CLK
13
and CLK
14
are employed instead of clock signals CLK
11
and CLK
12
as shown in FIG.
19
C.
FIGS. 20A-20D
are waveform diagrams of clock signals CLK
11
-CLK
14
.
FIG. 21
is a schematic waveform diagram of a potential VI of input node N
102
, a gate potential VG of N channel MOS transistor
103
, and potential VO of output node N
103
in each of charge pump unit circuits
102
.
1
,
102
.
3
, . . . ,
102
.N−1 of odd-numbered stages. Next, an operation of the positive charge pump circuit will be described with reference to
FIGS. 20A-20D
and FIG.
21
.
First, with reference to
FIGS. 20A-20D
, clock signal CLK
11
has a predetermined period and its duty factor is 50%. In
FIGS. 20A-20D
, clock signal CLK
11
attains an “H” level (a logical high level) from t
1
to t
3
and from t
5
to t
7
, whereas attains an “L” level (a logical low level) from t
3
to t
5
. Each of clock signals CLK
12
to CLK
14
has the same period as clock signal CLK
11
. Clock signal CLK
12
attains an “H” level in the latter half (that is, t
2
-t
3
and t
6
-t
7
) of a time period during which clock signal CLK
11
is atan “H” level and attains an “L” level in other time period. Clock signals CLK
13
and CLK
14
are a half period delayed from clock signals CLK
11
and CLK
12
, respectively.
Before t
1
, clock signals CLK
11
and CLK
12
are both at an “L” level. Therefore, VI and VG are both atan “H” level and capacitors
105
and
106
are charged with power supply voltage VCC.
At t
1
, clock signal CLK
11
is turned from an “L” level to an “H” level. Then the potential on input node N
102
is boosted by an amount of power supply voltage VCC via capacitor
105
and the boosted potential VI on input node N
102
is transferred to a gate of N channel MOS transistor
103
via resistance element
104
. Gate potential VG rises according to a curve determined by a time constant of the circuit.
At t
2
, clock signal CLK
12
is turned from an “L” level to an “H” level. Then gate potential VG is boosted by an amount of power supply voltage VCC via capacitor
106
. As a resistance of N channel MOS transistor
103
decreases, positive charge is transferred from input node N
102
to output node N
103
, whereby input potential VI falls and output potential VO rises.
At t
3
, clock signals CLK
11
and CLK
12
are turned from an “H” level to an “L” level. Thus the states of the signals return to the states before t
1
.
During the time period from t
3
to t
5
, clock signals CLK
11
and CLK
12
are held atan “L” level and charge pump unit circuits
102
.
1
,
102
.
3
, . . . ,
102
.N−1 of odd-numbered stages do not operate. During the time period from t
3
to t
5
, charge pump unit circuits
102
.
2
,
102
.
4
, . . . ,
102
.N of even-numbered stages operate in the same manner as charge pump unit circuits
102
.
1
,
102
.
3
, . . . ,
102
.N−1 of odd-numbered stages from t
1
to t
3
.
Thus in the positive charge pump circuit, charge pump unit circuits
102
.
1
,
102
.
3
, . . . ,
102
.N−1 of odd-numbered stages and charge pump unit circuits
102
.
2
,
102
.
4
, . . . ,
102
.N of even-numbered stages alternately operate in synchronization with clock signals CLK
11
to CLK
14
. Positive charge is supplied from each charge pump unit circuit to a charge pump unit circuit of the next stage. Positive charge is boosted in each charge pump unit circuit and charge pump unit circuit
102
.N of the final stage outputs a positive potential VO of a high level.
FIGS. 22A-22C
are circuit block diagrams showing a structure of a conventional negative charge pump circuit.
In
FIG. 22A
, the negative charge pump circuit includes a P channel MOS transistor
111
and N stages of charge pump unit circuits
112
.
1
to
112
.N connected in series. P channel MOS transistor
111
is diode connected between an input node of charge pump unit circuit
112
.
1
of the first stage and a line of a ground potential VSS.
Charge pump unit circuits
112
.
1
,
112
.
3
, . . . ,
112
.N−1 of odd-numbered stages supply negative charge to charge pump unit circuits
112
.
2
,
112
.
4
, . . . ,
112
.N located next to them, respectively, in synchronization with clock signals CLK
31
and CLK
32
. Charge pump unit circuits
112
.
2
,
112
.
4
,
112
.N−2 of even-numbered stages supply negative charge to charge pump unit circuits
112
.
3
,
112
.
5
, . . . ,
112
.N−1 located next to them and to an output node, respectively, in synchronization with clock signals CLK
33
and CLK
34
. An output potential of charge pump unit circuit
112
.N of the last stage is an output potential VO of the negative charge pump circuit.
Charge pump unit circuit
112
.
1
includes a P channel MOS transistor
113
, a resistance element
114
, and capacitors
115
and
116
as shown in
FIG. 22B. P
channel MOS transistor
113
is connected between an input node N
112
and an output node N
113
of charge pump unit circuit
112
.
1
. Resistance element
114
is connected between a gate of P channel MOS transistor
113
and input node N
112
. Capacitor
115
has one electrode receiving clock signal CLK
31
and another electrode connected to input node N
112
. Capacitor
116
has one electrode receiving clock signal CLK
32
and another electrode connected to the gate of N channel MOS transistor
113
.
Other charge pump unit circu

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