Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2002-11-04
2004-05-11
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S537000, C363S060000
Reexamination Certificate
active
06734717
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to charge pump circuits in semiconductor integrated circuits, and more specifically, to charge pump circuits with minimal output voltage losses and less stress on gate oxides of the MOS devices in the circuits.
2. Discussion of the Related Art
It is now usual to employ charge pump circuits in nonvolatile memories, for the purpose of preparing high voltages to conduct internal operations such as programming and erasing thereof. The charge pump circuits generate operational voltages higher than a power supply voltage provided from the external into the nonvolatile memory chips, by which the operational voltages induce charge tunneling effects through thin gate oxides in programming and erasing cell data.
Since the switched capacitor type of application in analog circuits, it has been mostly used the way of charge pump that was proposed by J. Dickson in IEEE Journal of Solid-State Circuits published on June 1976 (Vol. 11, pp. 374-378), entitled “On-chip high voltage generation in NMOS integrated circuits using an improved voltage multiplier technique.”
The Dickson's architecture is a construction of diode-coupled switches and pumping capacitors responding to two-phase clock signals. But, it has been well known that pumping circuits based on the Dickson's architecture fails to provide sufficient pumping when a power supply voltage becomes low, in which their output gains for boosting voltages decrease to an unusable condition.
The circuit shown in
FIG. 1
is one of trials to overcome the problems of the circuits based on the Dickson's architecture, disclosed in IEEE Journal of Solid-State Circuits on April 1998 (Vol. 33, pp. 592-597) by J. T. Wu and K. L. Chang), entitled “MOS charge pumps for low-voltage operation.”
Referring to
FIG. 1
, a first charge transfer switch T
11
is connected between an input terminal and a node Q
12
. The first charge transfer switch T
11
responds to a power supply voltage Vcc from the input terminal and a voltage at a node Q
11
. A first NMOS transistor N
11
is connected between the power supply voltage Vcc and the node Q
11
, and responds to a voltage at the node Q
12
. A first PMOS transistor P
11
is connected between the node Q
11
and a node Q
14
, and responds to the voltage at the node Q
12
. The bulk terminal of the first PMOS transistor P
11
is connected to the node Q
14
. A first capacitor C
11
is connected between a clock terminal and the node Q
12
, and responds to a clock signal &phgr; from the clock terminal to charge the node Q
12
.
A second charge transfer switch T
12
is connected between the nodes Q
12
and Q
14
, and responds to the voltage at the node Q
12
and a node Q
13
. A second NMOS transistor N
12
is connected between the nodes Q
12
and Q
13
, and responds to a voltage at the node Q
14
. A second PMOS transistor P
12
is connected between the node Q
13
and a node Q
16
, and responds to the voltage at the node Q
14
. The bulk terminal of the second PMOS transistor P
12
is connected to a node Q
16
. Also, a second capacitor C
12
is connected between a clock bar terminal and the node Q
14
, and responds to a clock bar signal &phgr;B from the clock bar terminal to charge the node Q
14
.
A third charge transfer switch T
13
is connected between the nodes Q
14
and Q
16
, and responds to a voltage at the node Q
14
and a node Q
15
. A third NMOS transistor N
13
is connected between the nodes Q
14
and Q
15
, and responds to a voltage at the node Q
16
. A third PMOS transistor P
13
is connected between the node Q
15
and a node Q
17
, and responds to the voltage at the node Q
16
. The bulk terminal of the third PMOS transistor P
13
is connected to a node Q
17
. Also, a third capacitor C
13
is connected to the clock terminal and the node Q
16
, and responds to the clock signal &phgr; from the clock terminal to charge the node Q
16
.
A fourth charge transfer switch T
14
is connected to the node Q
16
and an output terminal Vout, and responds to the voltages at nodes Q
16
and Q
17
. A capacitor C
14
is coupled between the node Q
17
and the clock bar terminal, and responds to a clock bar signal &phgr;B from the clock bar terminal. A capacitor C
15
is coupled between the output terminal Vout and a ground voltage terminal Vss.
In the operation of the charge pump circuit shown in
FIG. 1
, when the clock signal &phgr; is LOW and the clock bar signal &phgr;B is HIGH, the voltage at the node Q
12
is set to be a voltage lower than Vcc, and the voltages at the nodes Q
14
and Q
16
are set to Vcc+2&Dgr;V (&Dgr;V is a voltage increment). Meanwhile, the node Q
17
maintains a voltage of &Dgr;V. Since the voltage at the node Q
12
is lower than Vcc and the voltage at the node Q
14
is Vcc+2&Dgr;V, the PMOS transistor P
11
is turned ON and the voltage at the node Q
11
is set at Vcc+2&Dgr;V. In the meantime, as the voltage at the node Q
12
is held to be the voltage lower than Vcc, the NMOS transistor N
11
is turned OFF. Since the voltage at the node Q
11
is Vcc+2&Dgr;V, the charge transfer switch T
11
is turned ON. Thus, the node Q
12
maintains the voltage lower than Vcc.
To the contrary, when the clock signal &phgr; is HIGH and the clock bar signal &phgr;B is LOW, the voltages at the nodes Q
12
and Q
14
are set to Vcc+&Dgr;V and the node Q
16
rises up to Vcc+3&Dgr;V. While the voltage at the node Q
12
turns the NMOS transistor N
11
ON, the charge transfer switch T
11
is turned OFF because the voltage of the node Q
12
(i.e., Vcc+&Dgr;V) is higher than Vcc. At this time, the PMOS transistor P
11
is turned OFF. In the meantime, as the voltages at the nodes Q
14
and Q
16
are held at Vcc+&Dgr;V and Vcc+3&Dgr;V, respectively, the PMOS transistor P
12
is turned ON to make the voltage of the node Q
13
at Vcc+3&Dgr;V. And, the NMOS transistor N
12
is turned OFF because the voltages at the nodes, Q
12
and Q
14
, are identical each other. The voltage at the node Q
13
being Vcc+3&Dgr;V turns the charge transfer switch T
12
ON. Thus, the node Q
14
maintains Vcc+&Dgr;V.
Therefore, the nodes, Q
12
and Q
16
, are established respectively on Vcc+&Dgr;V and Vcc+3&Dgr;V by means of pumping in response to the clock signal &phgr; being HIGH, while the node Q
14
is pumped up to Vcc+2&Dgr;V in response to the clock bar signal &phgr;B being HIGH. That is, the clock signal &phgr; and the clock bar signal &phgr;B, alternately oscillate to maintain the output voltage at Vout at Vcc+3&Dgr;V.
As described above, in the conventional charge pump circuit, a front charge transfer switch responds to a high voltage generated from subsequent charge transfer switches. Therefore, in contrast to the circuits based on the Dickson's architecture, the less is the propagation loss for a pumping voltage, the better is the pumping efficiency of the circuit.
However, the conventional charge pump circuit shown in
FIG. 1
inevitably faces problems of a high voltage stress at gate oxide films of the MOS devices forming the charge transfer switches because the gate electrodes of the front charge transfer switches are driven by the high voltages generated from subsequent charge transfer switches. For instance, the charge transfer switch T
12
is turned on by the voltage of Vcc+3&Dgr;V at the node Q
16
, and thereby transfers the voltage of Vcc+&Dgr;V at the node Q
12
to the node Q
14
. At this time, a high voltage difference of 2&Dgr;V is between the nodes Q
16
and Q
12
and applied to gate oxide layers of the MOS devices of the charge transfer switch T
12
. Such a high voltage stress is disadvantageous to the reliability of the MOS devices.
Furthermore, as the MOS transistor acting T
14
as a transmission switch for the output terminal Vout is formed in a diode circuit, there is a voltage drop when a voltage level at the node Q
16
is transmitted to the output voltage Vout. Such a voltage drop is also disadvantageous to the reliability of the MOS devices.
SU
Callahan Timothy P.
Englund Terry L.
Hynix / Semiconductor Inc.
Morgan & Lewis & Bockius, LLP
LandOfFree
Charge pump circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Charge pump circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Charge pump circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3271245