Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-01-25
2003-02-04
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
Reexamination Certificate
active
06515535
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a charge pump circuit for use in a power source circuit or the like, and more particularly to a charge pump circuit realizing high efficiency and a large current output.
In the video appliances developed in recent years such as a video camera, digital still camera (DSC), a phone with DSC, etc., CCDs (Charge Coupled Devices) for acquiring an image are used. A CCD driving circuit for driving the CCDs requires a power source circuit which provides±high voltages (ten and several V) and large currents (several mA). At present, this high voltage is created using a switching regulator.
The switching regulator can create a high voltage with high performance, i.e. high power efficiency (output power/input power). However, this circuit has a defect of generating harmonic noise in current switching, and hence must use a power source circuit as a shield. It also requires a coil as an external component.
On the other hand, the charge pump circuit can create a high voltage with small noise, but conventionally has a defect of poor power efficiency. Therefore, this charge pump circuit cannot be used as it is as a power circuit for a portable appliance which needs excellent power efficiency. If a charge pump circuit with high performance is realized, it can contribute to miniaturization of the portable appliance.
A previously known most basic charge pump circuit is a Dickson charge pump circuit. The details of this circuit are described in a technical journal “John F. Dikson ‘On-chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique’ IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL.SC-11, NO.3 pp. 374-378 JUNE 1976.”
FIG. 11
is a schematic circuit diagram showing four-stage Dikson charge pump circuit. In
FIG. 11
, five diodes are connected in series. In
FIG. 11
, symbol C denotes a coupling capacitor, CL an output capacitor, and CLK and CLKB input clock pulses in opposite phases. Numeral
51
denotes a clock driver and
52
denotes a current load.
In a stable state, where a constant current Iout flows at the output, the input current supplied to the charge pump circuit includes a current coming from the input voltage Vin and current supplied from the clock driver. In disregard of a charging/discharging current to a stay capacitor, these currents are as follows. During the period of &PHgr;1=High and &PHgr;2=Low, the average current of 2 Iout flows in a direction of solid arrow. During the period of &PHgr;1=Low and &PHgr;2=High, the average current of 2 Iout flows in a direction of broken arrow. In a clock cycle, these average currents are Iout. In the stable sate, the boosted voltage Vout in the charge pump circuit can be expressed by Equation (1)
Vout=Vin−Vd+n
(
V&phgr;′−V
1
−Vd
) (1)
where V&phgr;′ denotes a voltage amplitude which is generated by a coupling capacitor owing to a change in a clock pulse; V
1
denotes a voltage drop generated by the output current Iout; Vin denotes an input voltage which is set at a power source voltage Vdd in “plus” voltage boosting and 0 V in “minus” voltage boosting; Vd denotes a forward bias diode voltage; and n denotes the number of stages of pumping. Further, V
1
and V&phgr;′ can be expressed by Equations (2) and (3)
V1
=
Iout
f
(
C
+
Cs
)
=
2
IoutT
/
2
C
+
Cs
(
2
)
V
φ
′
=
V
φ
C
C
+
Cs
(
3
)
where C denotes a clock coupling capacitance; Cs denotes a stay capacitance at each node, V&phgr; denotes a clock pulse amplitude; f denotes a clock pulse frequency; and T denotes a clock period. In disregard of the charging/discharging current flowing from the clock driver into the stay capacitor and assuming that Vin=Vdd, the power efficiency of the charge pump circuit can be expressed by Equation (4)
η
=
VoutIout
(
n
+
1
)
VddIout
=
Vout
(
n
+
1
)
Vdd
(
4
)
In this way, the charge pump circuit performs the voltage boosting in such a manner that a charge is successively transferred to a next stage using a diode as a charge transfer device. However, from the standpoint of mounting the charge transfer device in a MOS integrated circuit, a MOS transistor can be used more easily than a pn-junction diode. For this reason, using the MOS transistor in place of the diode as the charge transfer device has been proposed. In this case, in Equation 1, Vd represents a threshold voltage Vt of a MOS transistor.
Meanwhile, in order to remove the voltage loss corresponding to the threshold voltage to realize a high performance charge pump circuit, the impedance of the charge transfer MOS transistor must be reduced according to the value of Iout. For this purpose, it is efficient to optimize the channel width of the charge transfer MOS transistor and also increase the voltage Vgs between its gate and source to exceed the power source voltage Vdd. The charge pump which has realized this is described in detail in a technical article “Jieh-Tsorng Wu ‘MOS Charge Pumps for Low-Voltage Operation’ IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 33, NO. 4 APRIL 1998”.
As a result of the investigation of the charge pump circuit described in the above technical article, the inventors of this invention found the following problem. A circuit diagram of a charge pump circuit described in the article is shown in FIG.
12
. In
FIG. 12
, MD
1
-MD
4
which are diodes for initial setting of each pump node do not contribute a pumping operation. The feature of this circuit resides in that the charge transfer MOS transistors MS
1
-MS
3
is supplied with the gate/source voltage Vgs of 2 Vdd restored from the boosted voltage at the pumping node in the subsequent stage. However, it is difficult to supply the MOS transistor MS
4
in the last stage with Vgs of 2 Vdd so that the voltage loss is inevitably generated.
Another charge pump described in the above article is a dynamic charge pump as shown in FIG.
13
. In this circuit, in order to avoid reduction of Vgs of the MOS transistor MD
4
to Vdd+(Vdd−Vth) and that of the MOS transistor MDO to (Vdd−Vth), a high-voltage clock generator in a boot-strap system is used. All the MOS transistors for MS
1
-MS
4
are constructed of an N-channel type.
Where a current load is small, this system can be effectively used because the charge transfer MOS transistor is small in size and hence the gate stay capacitance is small. However, in order to realize the charge pump circuit which can provide a large current output, the channel width of the charge transfer MOS transistor must be as large as several milimeters (mm). As a result, the gate stay capacitance of the MOS transistor becomes large (several pF) so that it is difficult to create the clock of 2 Vdd by the boot strap system. Another technique must be proposed for applying the voltage not smaller than the power source voltage Vdd as a gate/source voltage of the charge transfer MOS transistor.
SUMMARY OF THE INVENTION
This invention has been accomplished in order to solve the above problem of the above prior art, and intends to provide a charge pump circuit which realizes high efficiency and provides a large output current. This invention also intends to assure the withstand voltage of a gate oxide film and realize optimum design of a charge transfer MOS transistor by setting the absolute value of the gate/source voltage Vgs of all the MOS transistors at 2 Vdd.
According to first aspect of the invention, a charge pump circuit comprises: (n+2) number of charge transfer MOS transistors connected in series, to an initial stage of which is supplied with a prescribed input voltage; coupling capacitors one terminals of which are connected to connecting points between the charge transfer MOS transistors, respectively; and a clock driver for supplying clock pulses opposite to each other alternately to the other terminals of the coupling capacitors, thereby producing a positive boosted voltage, wherein the charge transf
Cunningham Terry D.
Fish & Richardson P.C.
Sanyo Electric Co,. Ltd.
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