Charge pump circuit

Details Charge pump circuit Charge pump circuit

2002-09-04

2003-12-30

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C363S060000

Reexamination Certificate

active

06670844

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a charge pump circuit which is used for boosting a voltage supplied to an integrated circuit from an external voltage source and supplying the boosted voltage to an internal circuit.
2. Prior Art
As a conventional charge pump, there is known one, for example, which is disclosed in Japanese Examined Patent Publication No. 68188/1993. As shown in
FIG. 2
, this charge pump includes MOS transistors m
1
-m
6
each having its drain and gate interconnected via a so-called diode connection and having respective sources and drains thereof interconnected thereby defining multiple stages interconnected in cascade, and capacitor elements c
1
to c
6
individually connected to the respective sources of the MOS transistors m
1
-m
6
, and is designed to obtain a boosted voltage V
o
from the final stage MOS transistor m
6
by applying an input voltage V
i
to the drain and gate of the initial stage MOS transistor m
1
and then alternately applying a clock signal &phgr; and an inverted clock signal &phgr;
n
to the MOS transistors m
1
-m
6
via the respective capacitor elements c
1
-c
6
. The conventional charge pump has an arrangement wherein some initial stages on an input side, such as MOS transistors m
1
, m
2
for example, are comprised of an enhancement-type transistor; intermediate stages, MOS transistors m
3
, m
4
, are comprised of a transistor having a threshold voltage of 0V; and final stages, MOS transistors m
5
, m
6
, are comprised of a depression-type transistor.
A threshold voltage for each of the transistors is expressed as V
th
+
&Dgr;
V
th(B)
, where V
th
denotes a threshold voltage of the transistor when a substrate bias voltage is at 0V; and
&Dgr;
V
th(B)
denotes an amount of variation of the threshold voltage due to the substrate bias voltage. Assuming that the clock signal &phgr; is at high level, a potential at Point A in
FIG. 2
is expressed as V
i
−(V
th
+
&Dgr;
V
th(i)
) (=V
A0
), where V
i
denotes the input voltage. At this time, the inverted clock signal &phgr;
n
rises, so that a potential at Point B is at V&phgr; (=V
B0
). On the other hand, a potential at Point C is expressed as V
i
−(V
th
+
&Dgr;
V
th(i)
)(=V
C0
)
Next, the succeeding clock signal &phgr; rises so that the potential at Point A is expressed as V
i
−(V
th
+&Dgr;V
th(i)
)+V&phgr;(=V
A1
), whereas the potential at Point B is expressed as V
A1
−(V
th
+
&Dgr;
V
th(A1)
)(=V
B1
). At this time, the potential at Point C is expressed as V
C0
+V&phgr;(=V
C1
). When the clock signal &phgr; rises again, the potential at Point A is returned to V
A0
, whereas the potential at Point B is expressed as V
B1
+V&phgr; (=V
B2
) and the potential at Point C is expressed as V
B1
−(V
th
+
&Dgr;
V
th(B1)
)(=V
C2
). Subsequently, when the clock signal &phgr; rises again, the potential at Point A is V
A1
, whereas the potential at Point B is returned to V
B1
and the potential at Point C is expressed as V
C2
+V&phgr;.
Although the charge pump is adapted to gradually boost the input voltage by repeating the above operations in cycles, the value of
&Dgr;
V
B
is progressively increased toward the succeeding stages with respect to the input side so that the efficiency of boosting the voltage is correspondingly lowered. As a solution to this drawback, the intermediate stages and the succeeding stages employ the transistor having the threshold voltage of 0V and the device having a low V
th
, such as the depression-type transistor or the like, thereby providing for the voltage boost involving little decrease in the efficiency of boosting the voltage.
SUMMARY OF THE INVENTION
However, the conventional charge pump employs three types of devices which include the enhancement transistor defining the initial stage with respect to the input side; the transistor with the V
th
of 0V defining the intermediate stage; and the depression transistor defining the final stage. The use of the plural types of devices leads to a difficult implementation of each of the devices in the fabrication procedure and also entails a lowered reliability of the circuit. Furthermore, a circuit simulation uses plural models, which leads to an inability to perform the simulation with high accuracies.
In this connection, the invention is directed to a charge pump circuit comprised of one type of device thereby overcoming the above problem.
A charge pump circuit according to the invention comprises: a plurality of transistors individually having a diode connection configuration and defining multiple stages interconnected in cascade, and capacitor elements connected to the respective transistors, and is designed to obtain a boosted voltage from a final stage of the transistors by inputting a given voltage to an initial stage of the transistors and then alternately applying a clock signal and an inverted clock signal to the plurality of transistors via the respective capacitor elements, wherein the plurality of transistors are of depression type, and wherein a predetermined number of stages of the transistors have a greater gate length than the succeeding stages of the transistors.


REFERENCES:
patent: 5905291 (1999-05-01), Utsunomiya et al.
patent: 6603346 (2003-08-01), Sawada et al.
patent: 2002/0190689 (2002-12-01), Nakamura et al.
patent: 2003/0011419 (2003-01-01), Moriyama

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